43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
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#define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
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/* macros related to interrupt handling */
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#define XTENSA_IRQ_NUM_SHIFT 0
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#define CAVS_IRQ_NUM_SHIFT 8
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#define XTENSA_IRQ_NUM_MASK 0xff
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#define CAVS_IRQ_NUM_MASK 0xff
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/*
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* IRQs are mapped on 2 levels. 3rd and 4th level are left as 0x00.
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*
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* 1. Peripheral Register bit offset.
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* 2. CAVS logic bit offset.
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*/
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#define XTENSA_IRQ_NUMBER(_irq) \
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((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
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#define CAVS_IRQ_NUMBER(_irq) \
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(((_irq >> CAVS_IRQ_NUM_SHIFT) & CAVS_IRQ_NUM_MASK) - 1)
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/* Macro that aggregates the bi-level interrupt into an IRQ number */
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#define SOC_AGGREGATE_IRQ(cavs_irq, core_irq) \
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( \
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((core_irq & XTENSA_IRQ_NUM_MASK) << XTENSA_IRQ_NUM_SHIFT) | \
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(((cavs_irq + 1) & CAVS_IRQ_NUM_MASK) << CAVS_IRQ_NUM_SHIFT) \
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)
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#define CAVS_L2_AGG_INT_LEVEL2 DT_IRQN(DT_INST(0, intel_cavs_intc))
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#define CAVS_L2_AGG_INT_LEVEL3 DT_IRQN(DT_INST(1, intel_cavs_intc))
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#define CAVS_L2_AGG_INT_LEVEL4 DT_IRQN(DT_INST(2, intel_cavs_intc))
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#define CAVS_L2_AGG_INT_LEVEL5 DT_IRQN(DT_INST(3, intel_cavs_intc))
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#define CAVS_ICTL_INT_CPU_OFFSET(x) (0x40 * x)
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#endif
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