132 lines
2.8 KiB
YAML
132 lines
2.8 KiB
YAML
#
|
|
# Copyright (c) 2019 Vestas Wind Systems A/S
|
|
#
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
#
|
|
|
|
title: NXP Kinetis SCG (System Clock Generator)
|
|
|
|
description: >
|
|
This is a representation of the NXP Kinetis SCG IP node
|
|
|
|
inherits:
|
|
!include base.yaml
|
|
|
|
properties:
|
|
compatible:
|
|
constraint: "nxp,kinetis-scg"
|
|
|
|
reg:
|
|
category: required
|
|
|
|
label:
|
|
category: required
|
|
|
|
clk-divider-slow:
|
|
type: int
|
|
description: system clock to slow clock divider
|
|
category: required
|
|
|
|
clk-divider-bus:
|
|
type: int
|
|
description: system clock to bus clock divider
|
|
category: required
|
|
|
|
clk-divider-core:
|
|
type: int
|
|
description: system clock to core clock divider
|
|
category: required
|
|
|
|
clk-source:
|
|
type: int
|
|
description: system clock source
|
|
category: optional
|
|
|
|
sosc-freq:
|
|
type: int
|
|
description: system oscillator (e.g. xtal) frequency
|
|
category: optional
|
|
|
|
sosc-mode:
|
|
type: int
|
|
description: system oscillator mode
|
|
category: optional
|
|
|
|
sosc-divider-1:
|
|
type: int
|
|
description: system oscillator divider 1
|
|
category: optional
|
|
|
|
sosc-divider-2:
|
|
type: int
|
|
description: system oscillator divider 2
|
|
category: optional
|
|
|
|
sirc-range:
|
|
type: int
|
|
description: slow internal reference clock range in MHz
|
|
category: required
|
|
|
|
sirc-divider-1:
|
|
type: int
|
|
description: slow internal reference clock divider 1
|
|
category: required
|
|
|
|
sirc-divider-2:
|
|
type: int
|
|
description: slow internal reference clock divider 2
|
|
category: required
|
|
|
|
firc-range:
|
|
type: int
|
|
description: fast internal reference clock range in MHz
|
|
category: required
|
|
|
|
firc-divider-1:
|
|
type: int
|
|
description: fast internal reference clock divider 1
|
|
category: required
|
|
|
|
firc-divider-2:
|
|
type: int
|
|
description: fast internal reference clock divider 2
|
|
category: required
|
|
|
|
spll-source:
|
|
type: int
|
|
description: system phase-locked loop clock source
|
|
category: required
|
|
|
|
spll-divider-pre:
|
|
type: int
|
|
description: system phase-locked loop reference clock divider
|
|
category: required
|
|
|
|
spll-multiplier:
|
|
type: int
|
|
description: system phase-locked loop reference clock multiplier
|
|
category: required
|
|
|
|
spll-divider-1:
|
|
type: int
|
|
description: system phase-locked loop divider 1
|
|
category: required
|
|
|
|
spll-divider-2:
|
|
type: int
|
|
description: system phase-locked loop divider 2
|
|
category: required
|
|
|
|
clkout-source:
|
|
type: int
|
|
description: clockout clock source
|
|
category: optional
|
|
|
|
"#clock-cells":
|
|
type: int
|
|
category: required
|
|
description: should be 1.
|
|
|
|
"#cells":
|
|
- name
|