29 lines
582 B
Plaintext
29 lines
582 B
Plaintext
# Copyright (c) 2016 Open-RnD Sp. z o.o.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# Copyright (c) 2023 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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if SOC_XTENSA_DC233C
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config SOC_XTENSA_DC233C
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select XTENSA_GEN_HANDLERS
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config XTENSA_MMU_NUM_L2_TABLES
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int
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default 48 if XTENSA_MMU
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# Both SRAM_OFFSET and KERNEL_VM_OFFSET are set at 1MB.
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# This is to allow VECBASE to be mapped permanently
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# via TLB way 4 (which covers 1MB).
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config SRAM_OFFSET
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hex
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default 0x100000 if XTENSA_MMU
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default 0x2400
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config KERNEL_VM_OFFSET
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hex
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default 0x100000
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endif
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