534 lines
12 KiB
Plaintext
534 lines
12 KiB
Plaintext
/*
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* Copyright 2018 Foundries.io Ltd
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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zephyr,entropy = &trng;
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zephyr,flash-controller = &ftfe;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "openisa,ri5cy", "riscv";
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riscv,isa = "rv32imc_zicsr_zifencei";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "openisa,zero-ri5cy", "riscv";
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riscv,isa = "rv32imc_zicsr_zifencei";
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reg = <1>;
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};
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};
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m4_dtcm: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 0x30000>;
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};
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m0_tcm: memory@9000000 {
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compatible = "mmio-sram";
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reg = <0x09000000 0x20000>;
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};
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/* Dummy pinctrl node, filled with pin mux options at board level */
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pinctrl: pinctrl {
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compatible = "openisa,rv32m1-pinctrl";
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status = "okay";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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pcc0: clock-controller@4002b000 {
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compatible = "openisa,rv32m1-pcc";
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reg = <0x4002b000 0x200>;
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#clock-cells = <1>;
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};
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pcc1: clock-controller@41027000 {
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compatible = "openisa,rv32m1-pcc";
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reg = <0x41027000 0x200>;
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#clock-cells = <1>;
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};
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event0: interrupt-controller@e0041000 {
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compatible = "openisa,rv32m1-event-unit";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0xe0041000 0x88>;
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};
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event1: interrupt-controller@4101f000 {
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compatible = "openisa,rv32m1-event-unit";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0x4101f000 0x88>;
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};
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intmux0: intmux@4004f000 {
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compatible = "openisa,rv32m1-intmux";
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reg = <0x4004f000 0x200>;
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clocks = <&pcc0 0x13c>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x4004f000 0x200>;
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intmux0_ch0: interrupt-controller@0 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH0_IRQ>;
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reg = <0x0 0x40>;
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status = "disabled";
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};
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intmux0_ch1: interrupt-controller@40 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH1_IRQ>;
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reg = <0x40 0x40>;
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status = "disabled";
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};
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intmux0_ch2: interrupt-controller@80 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH2_IRQ>;
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reg = <0x80 0x40>;
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status = "disabled";
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};
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intmux0_ch3: interrupt-controller@c0 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH3_IRQ>;
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reg = <0xc0 0x40>;
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status = "disabled";
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};
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intmux0_ch4: interrupt-controller@100 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH4_IRQ>;
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reg = <0x100 0x40>;
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status = "disabled";
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};
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intmux0_ch5: interrupt-controller@140 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH5_IRQ>;
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reg = <0x140 0x40>;
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status = "disabled";
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};
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intmux0_ch6: interrupt-controller@180 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH6_IRQ>;
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reg = <0x180 0x40>;
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status = "disabled";
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};
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intmux0_ch7: interrupt-controller@1c0 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH7_IRQ>;
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reg = <0x1c0 0x40>;
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status = "disabled";
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};
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};
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intmux1: intmux@41022000 {
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compatible = "openisa,rv32m1-intmux";
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reg = <0x41022000 0x20>;
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clocks = <&pcc1 0x88>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x41022000 0x200>;
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intmux1_ch0: interrupt-controller@0 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH0_IRQ>;
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reg = <0x0 0x40>;
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status = "disabled";
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};
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intmux1_ch1: interrupt-controller@40 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH1_IRQ>;
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reg = <0x40 0x40>;
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status = "disabled";
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};
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intmux1_ch2: interrupt-controller@80 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH2_IRQ>;
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reg = <0x80 0x40>;
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status = "disabled";
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};
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intmux1_ch3: interrupt-controller@c0 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH3_IRQ>;
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reg = <0xc0 0x40>;
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status = "disabled";
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};
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intmux1_ch4: interrupt-controller@100 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH4_IRQ>;
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reg = <0x100 0x40>;
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status = "disabled";
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};
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intmux1_ch5: interrupt-controller@140 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH5_IRQ>;
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reg = <0x140 0x40>;
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status = "disabled";
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};
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intmux1_ch6: interrupt-controller@180 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH6_IRQ>;
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reg = <0x180 0x40>;
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status = "disabled";
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};
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intmux1_ch7: interrupt-controller@1c0 {
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compatible = "openisa,rv32m1-intmux-ch";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts = <INTMUX_CH7_IRQ>;
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reg = <0x1c0 0x40>;
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status = "disabled";
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};
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};
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lptmr0: timer@40032000 {
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compatible = "openisa,rv32m1-lptmr";
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reg = <0x40032000 0x10>;
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};
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lptmr1: timer@40033000 {
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compatible = "openisa,rv32m1-lptmr";
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reg = <0x40033000 0x10>;
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};
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lptmr2: timer@4102b000 {
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compatible = "openisa,rv32m1-lptmr";
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reg = <0x4102b000 0x10>;
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};
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porta: pinmux@40046000 {
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compatible = "openisa,rv32m1-pinmux";
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reg = <0x40046000 0xd0>;
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clocks = <&pcc0 0x118>;
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};
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portb: pinmux@40047000 {
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compatible = "openisa,rv32m1-pinmux";
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reg = <0x40047000 0xd0>;
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clocks = <&pcc0 0x11c>;
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};
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portc: pinmux@40048000 {
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compatible = "openisa,rv32m1-pinmux";
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reg = <0x40048000 0xd0>;
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clocks = <&pcc0 0x120>;
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};
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portd: pinmux@40049000 {
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compatible = "openisa,rv32m1-pinmux";
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reg = <0x40049000 0xd0>;
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clocks = <&pcc0 0x124>;
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};
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porte: pinmux@41037000 {
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compatible = "openisa,rv32m1-pinmux";
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reg = <0x41037000 0xd0>;
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clocks = <&pcc1 0xdc>;
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};
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gpioa: gpio@48020000 {
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compatible = "openisa,rv32m1-gpio";
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reg = <0x48020000 0x14>;
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gpio-controller;
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#gpio-cells = <2>;
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openisa,rv32m1-port = <&porta>;
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};
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gpiob: gpio@48020040 {
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compatible = "openisa,rv32m1-gpio";
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reg = <0x48020040 0x14>;
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gpio-controller;
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#gpio-cells = <2>;
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openisa,rv32m1-port = <&portb>;
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};
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gpioc: gpio@48020080 {
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compatible = "openisa,rv32m1-gpio";
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reg = <0x48020080 0x14>;
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gpio-controller;
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#gpio-cells = <2>;
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openisa,rv32m1-port = <&portc>;
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};
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gpiod: gpio@480200c0 {
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compatible = "openisa,rv32m1-gpio";
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reg = <0x480200c0 0x14>;
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gpio-controller;
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#gpio-cells = <2>;
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openisa,rv32m1-port = <&portd>;
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};
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gpioe: gpio@4100f000 {
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compatible = "openisa,rv32m1-gpio";
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reg = <0x4100f000 0x14>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&pcc1 0x3c>;
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openisa,rv32m1-port = <&porte>;
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};
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lpuart0: lpuart@40042000 {
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compatible = "openisa,rv32m1-lpuart";
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reg = <0x40042000 0x2c>;
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clocks = <&pcc0 0x108>;
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status = "disabled";
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};
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lpuart1: lpuart@40043000 {
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compatible = "openisa,rv32m1-lpuart";
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reg = <0x40043000 0x2c>;
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clocks = <&pcc0 0x10c>;
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status = "disabled";
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};
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lpuart2: lpuart@40044000 {
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compatible = "openisa,rv32m1-lpuart";
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reg = <0x40044000 0x2c>;
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clocks = <&pcc0 0x110>;
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status = "disabled";
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};
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lpuart3: lpuart@41036000 {
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compatible = "openisa,rv32m1-lpuart";
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reg = <0x41036000 0x2c>;
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clocks = <&pcc0 0xd8>;
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status = "disabled";
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};
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lpi2c0: lpi2c@4003a000 {
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compatible = "openisa,rv32m1-lpi2c";
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reg = <0x4003a000 0x170>;
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clocks = <&pcc0 0xe8>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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lpi2c1: lpi2c@4003b000 {
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compatible = "openisa,rv32m1-lpi2c";
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reg = <0x4003b000 0x170>;
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clocks = <&pcc0 0xec>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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lpi2c2: lpi2c@4003c000 {
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compatible = "openisa,rv32m1-lpi2c";
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reg = <0x4003c000 0x170>;
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clocks = <&pcc0 0xf0>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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lpi2c3: lpi2c@4102e000 {
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compatible = "openisa,rv32m1-lpi2c";
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reg = <0x4102e000 0x170>;
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clocks = <&pcc1 0xb8>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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lpspi0: spi@4003f000 {
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compatible = "openisa,rv32m1-lpspi";
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reg = <0x4003f000 0x78>;
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status = "disabled";
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clocks = <&pcc0 0xfc>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpspi1: spi@40040000 {
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compatible = "openisa,rv32m1-lpspi";
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reg = <0x40040000 0x78>;
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status = "disabled";
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clocks = <&pcc0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpspi2: spi@40041000 {
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compatible = "openisa,rv32m1-lpspi";
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reg = <0x40041000 0x78>;
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status = "disabled";
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clocks = <&pcc0 0x104>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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lpspi3: spi@41035000 {
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compatible = "openisa,rv32m1-lpspi";
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reg = <0x41035000 0x78>;
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status = "disabled";
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clocks = <&pcc1 0xd4>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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generic_fsk: generic_fsk@41033000 {
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compatible = "openisa,rv32m1-genfsk";
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reg = <0x41033000 0x90>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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tpm0: pwm@40035000 {
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compatible = "openisa,rv32m1-tpm";
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reg = <0x40035000 0x88>;
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clocks = <&pcc0 0xd4>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tpm1: pwm@40036000 {
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compatible = "openisa,rv32m1-tpm";
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reg = <0x40036000 0x88>;
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clocks = <&pcc0 0xd8>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tpm2: pwm@40037000 {
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compatible = "openisa,rv32m1-tpm";
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reg = <0x40037000 0x88>;
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clocks = <&pcc0 0xdc>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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trng: random@41029000{
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compatible = "openisa,rv32m1-trng";
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reg = <0x41029000 0x1000>;
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status = "okay";
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interrupts = <13 0>;
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};
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tpm3: pwm@4102d000 {
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compatible = "openisa,rv32m1-tpm";
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reg = <0x4102d000 0x88>;
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clocks = <&pcc1 0xb4>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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ftfe: flash-controller@40023000 {
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compatible = "openisa,rv32m1-ftfe";
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reg = <0x40023000 0x18>;
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#address-cells = <1>;
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#size-cells = <1>;
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m4_flash: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 0x100000>;
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erase-block-size = <4096>;
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write-block-size = <8>;
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};
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m0_flash: flash@1000000 {
|
|
compatible = "soc-nv-flash";
|
|
reg = <0x01000000 0x40000>;
|
|
erase-block-size = <4096>;
|
|
write-block-size = <8>;
|
|
};
|
|
};
|
|
|
|
bt_hci_controller: bt_hci_controller {
|
|
compatible = "zephyr,bt-hci-ll-sw-split";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|