680 lines
16 KiB
C
680 lines
16 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include <soc/dport_reg.h>
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#include <soc/i2c_reg.h>
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#include <rom/gpio.h>
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#include <soc/gpio_sig_map.h>
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#include <soc.h>
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#include <errno.h>
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#include <gpio.h>
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#include <gpio/gpio_esp32.h>
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#include <i2c.h>
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#include <misc/util.h>
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#include <string.h>
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/* Number of entries in hardware command queue */
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#define I2C_ESP32_NUM_CMDS 16
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/* Number of bytes in hardware FIFO */
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#define I2C_ESP32_BUFFER_SIZE 32
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#define I2C_ESP32_TIMEOUT_MS 100
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#define I2C_ESP32_SPIN_THRESHOLD 600
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#define I2C_ESP32_YIELD_THRESHOLD (I2C_ESP32_SPIN_THRESHOLD / 2)
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#define I2C_ESP32_TIMEOUT \
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((I2C_ESP32_YIELD_THRESHOLD) + (I2C_ESP32_SPIN_THRESHOLD))
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enum i2c_esp32_opcodes {
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I2C_ESP32_OP_RSTART,
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I2C_ESP32_OP_WRITE,
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I2C_ESP32_OP_READ,
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I2C_ESP32_OP_STOP,
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I2C_ESP32_OP_END
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};
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struct i2c_esp32_cmd {
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u32_t num_bytes : 8;
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u32_t ack_en : 1;
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u32_t ack_exp : 1;
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u32_t ack_val : 1;
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u32_t opcode : 3;
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u32_t reserved : 17;
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u32_t done : 1;
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};
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struct i2c_esp32_data {
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u32_t dev_config;
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u16_t address;
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struct k_sem fifo_sem;
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struct k_sem transfer_sem;
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};
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typedef void (*irq_connect_cb)(void);
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struct i2c_esp32_config {
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int index;
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irq_connect_cb connect_irq;
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const struct {
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int sda_out;
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int sda_in;
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int scl_out;
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int scl_in;
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} sig;
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const struct {
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int scl;
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int sda;
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} pins;
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const struct esp32_peripheral peripheral;
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const struct {
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bool tx_lsb_first;
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bool rx_lsb_first;
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} mode;
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const struct {
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int source;
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int line;
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} irq;
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const u32_t default_config;
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};
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static int i2c_esp32_configure_pins(int pin, int matrix_out, int matrix_in)
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{
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const int pin_mode = GPIO_DIR_OUT |
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GPIO_DS_DISCONNECT_LOW |
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GPIO_PUD_PULL_UP;
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const char *device_name = gpio_esp32_get_gpio_for_pin(pin);
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struct device *gpio;
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int ret;
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if (!device_name) {
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return -EINVAL;
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}
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gpio = device_get_binding(device_name);
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if (!gpio) {
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return -EINVAL;
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}
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ret = gpio_pin_configure(gpio, pin, pin_mode);
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if (ret < 0) {
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return ret;
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}
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ret = gpio_pin_write(gpio, pin, 1);
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if (ret < 0) {
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return ret;
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}
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esp32_rom_gpio_matrix_out(pin, matrix_out, false, false);
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esp32_rom_gpio_matrix_in(pin, matrix_in, false);
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return 0;
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}
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static int i2c_esp32_configure_speed(const struct i2c_esp32_config *config,
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u32_t speed)
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{
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static const u32_t speed_to_freq_tbl[] = {
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[I2C_SPEED_STANDARD] = KHZ(100),
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[I2C_SPEED_FAST] = KHZ(400),
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[I2C_SPEED_FAST_PLUS] = MHZ(1),
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[I2C_SPEED_HIGH] = 0,
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[I2C_SPEED_ULTRA] = 0
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};
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u32_t freq_hz = speed_to_freq_tbl[speed];
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u32_t period;
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if (!freq_hz) {
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return -ENOTSUP;
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}
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period = (APB_CLK_FREQ / freq_hz) / 2U;
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esp32_set_mask32(period << I2C_SCL_LOW_PERIOD_S,
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I2C_SCL_LOW_PERIOD_REG(config->index));
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esp32_set_mask32(period << I2C_SCL_HIGH_PERIOD_S,
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I2C_SCL_HIGH_PERIOD_REG(config->index));
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period /= 2U; /* Set hold and setup times to 1/2th of period */
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esp32_set_mask32(period << I2C_SCL_START_HOLD_TIME_S,
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I2C_SCL_START_HOLD_REG(config->index));
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esp32_set_mask32(period << I2C_SCL_RSTART_SETUP_TIME_S,
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I2C_SCL_RSTART_SETUP_REG(config->index));
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esp32_set_mask32(period << I2C_SCL_STOP_HOLD_TIME_S,
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I2C_SCL_STOP_HOLD_REG(config->index));
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esp32_set_mask32(period << I2C_SCL_STOP_SETUP_TIME_S,
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I2C_SCL_STOP_SETUP_REG(config->index));
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period /= 2U; /* Set sample and hold times to 1/4th of period */
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esp32_set_mask32(period << I2C_SDA_HOLD_TIME_S,
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I2C_SDA_HOLD_REG(config->index));
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esp32_set_mask32(period << I2C_SDA_SAMPLE_TIME_S,
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I2C_SDA_SAMPLE_REG(config->index));
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return 0;
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}
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static int i2c_esp32_configure(struct device *dev, u32_t dev_config)
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{
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const struct i2c_esp32_config *config = dev->config->config_info;
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struct i2c_esp32_data *data = dev->driver_data;
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unsigned int key = irq_lock();
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u32_t v = 0U;
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int ret;
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ret = i2c_esp32_configure_pins(config->pins.scl,
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config->sig.scl_out,
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config->sig.scl_in);
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if (ret < 0) {
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return ret;
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}
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ret = i2c_esp32_configure_pins(config->pins.sda,
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config->sig.sda_out,
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config->sig.sda_in);
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if (ret < 0) {
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return ret;
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}
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esp32_enable_peripheral(&config->peripheral);
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/* MSB or LSB first is configurable for both TX and RX */
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if (config->mode.tx_lsb_first) {
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v |= I2C_TX_LSB_FIRST;
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}
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if (config->mode.rx_lsb_first) {
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v |= I2C_RX_LSB_FIRST;
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}
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if (dev_config & I2C_MODE_MASTER) {
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v |= I2C_MS_MODE;
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sys_write32(0, I2C_SLAVE_ADDR_REG(config->index));
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} else {
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u32_t addr = (data->address & I2C_SLAVE_ADDR_V);
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if (dev_config & I2C_ADDR_10_BITS) {
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addr |= I2C_ADDR_10BIT_EN;
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}
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sys_write32(addr << I2C_SLAVE_ADDR_S,
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I2C_SLAVE_ADDR_REG(config->index));
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/* Before setting up FIFO and interrupts, stop transmission */
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sys_clear_bit(I2C_CTR_REG(config->index), I2C_TRANS_START_S);
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/* Byte after address isn't the offset address in slave RAM */
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sys_clear_bit(I2C_FIFO_CONF_REG(config->index),
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I2C_FIFO_ADDR_CFG_EN_S);
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}
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/* Use open-drain for clock and data pins */
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v |= (I2C_SCL_FORCE_OUT | I2C_SDA_FORCE_OUT);
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v |= I2C_CLK_EN;
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sys_write32(v, I2C_CTR_REG(config->index));
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ret = i2c_esp32_configure_speed(config, I2C_SPEED_GET(dev_config));
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if (ret < 0) {
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goto out;
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}
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/* Use FIFO to transmit data */
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sys_clear_bit(I2C_FIFO_CONF_REG(config->index), I2C_NONFIFO_EN_S);
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v = CONFIG_I2C_ESP32_TIMEOUT & I2C_TIME_OUT_REG;
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sys_write32(v << I2C_TIME_OUT_REG_S, I2C_TO_REG(config->index));
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/* Enable interrupt types handled by the ISR */
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sys_write32(I2C_ACK_ERR_INT_ENA_M |
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I2C_TIME_OUT_INT_ENA_M |
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I2C_TRANS_COMPLETE_INT_ENA_M |
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I2C_ARBITRATION_LOST_INT_ENA_M,
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I2C_INT_ENA_REG(config->index));
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irq_enable(config->irq.line);
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out:
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irq_unlock(key);
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return ret;
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}
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static inline void i2c_esp32_reset_fifo(const struct i2c_esp32_config *config)
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{
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u32_t reg = I2C_FIFO_CONF_REG(config->index);
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/* Writing 1 and then 0 to these bits will reset the I2C fifo */
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esp32_set_mask32(I2C_TX_FIFO_RST | I2C_RX_FIFO_RST, reg);
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esp32_clear_mask32(I2C_TX_FIFO_RST | I2C_RX_FIFO_RST, reg);
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}
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static int i2c_esp32_spin_yield(int *counter)
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{
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*counter = *counter + 1;
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if (*counter > I2C_ESP32_TIMEOUT) {
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return -ETIMEDOUT;
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}
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if (*counter > I2C_ESP32_SPIN_THRESHOLD) {
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k_yield();
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}
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return 0;
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}
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static int i2c_esp32_transmit(struct device *dev)
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{
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const struct i2c_esp32_config *config = dev->config->config_info;
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struct i2c_esp32_data *data = dev->driver_data;
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u32_t status;
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/* Start transmission and wait for the ISR to give the semaphore */
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sys_set_bit(I2C_CTR_REG(config->index), I2C_TRANS_START_S);
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if (k_sem_take(&data->fifo_sem, I2C_ESP32_TIMEOUT_MS) < 0) {
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return -ETIMEDOUT;
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}
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status = sys_read32(I2C_INT_RAW_REG(config->index));
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if (status & (I2C_ARBITRATION_LOST_INT_RAW | I2C_ACK_ERR_INT_RAW)) {
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return -EIO;
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}
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if (status & I2C_TIME_OUT_INT_RAW) {
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int i2c_esp32_wait(struct device *dev,
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volatile struct i2c_esp32_cmd *wait_cmd)
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{
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const struct i2c_esp32_config *config = dev->config->config_info;
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int counter = 0;
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int ret;
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if (wait_cmd) {
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while (!wait_cmd->done) {
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ret = i2c_esp32_spin_yield(&counter);
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if (ret < 0) {
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return ret;
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}
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}
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}
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/* Wait for I2C bus to finish its business */
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while (sys_read32(I2C_SR_REG(config->index)) & I2C_BUS_BUSY) {
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ret = i2c_esp32_spin_yield(&counter);
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if (ret < 0) {
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return ret;
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}
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}
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return 0;
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}
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static int i2c_esp32_transmit_wait(struct device *dev,
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volatile struct i2c_esp32_cmd *wait_cmd)
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{
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int ret;
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ret = i2c_esp32_transmit(dev);
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if (!ret) {
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return i2c_esp32_wait(dev, wait_cmd);
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}
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return ret;
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}
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static volatile struct i2c_esp32_cmd *
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i2c_esp32_write_addr(struct device *dev,
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volatile struct i2c_esp32_cmd *cmd,
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struct i2c_msg *msg,
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u16_t addr)
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{
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const struct i2c_esp32_config *config = dev->config->config_info;
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struct i2c_esp32_data *data = dev->driver_data;
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u32_t addr_len = 1U;
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i2c_esp32_reset_fifo(config);
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sys_write32(addr & I2C_FIFO_RDATA, I2C_DATA_APB_REG(config->index));
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if (data->dev_config & I2C_ADDR_10_BITS) {
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sys_write32(I2C_DATA_APB_REG(config->index),
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(addr >> 8) & I2C_FIFO_RDATA);
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addr_len++;
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}
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if ((msg->flags & I2C_MSG_RW_MASK) != I2C_MSG_WRITE) {
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*cmd++ = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_WRITE,
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.ack_en = true,
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.num_bytes = addr_len,
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};
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} else {
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msg->len += addr_len;
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}
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return cmd;
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}
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static int i2c_esp32_read_msg(struct device *dev, u16_t addr,
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struct i2c_msg msg)
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{
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const struct i2c_esp32_config *config = dev->config->config_info;
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volatile struct i2c_esp32_cmd *cmd =
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(void *)I2C_COMD0_REG(config->index);
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u32_t i;
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int ret;
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/* Set the R/W bit to R */
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addr |= BIT(0);
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*cmd++ = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_RSTART
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};
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cmd = i2c_esp32_write_addr(dev, cmd, &msg, addr);
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for (; msg.len; cmd = (void *)I2C_COMD0_REG(config->index)) {
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volatile struct i2c_esp32_cmd *wait_cmd = NULL;
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u32_t to_read = MIN(I2C_ESP32_BUFFER_SIZE, msg.len - 1);
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/* Might be the last byte, in which case, `to_read` will
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* be 0 here. See comment below.
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*/
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if (to_read) {
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*cmd++ = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_READ,
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.num_bytes = to_read,
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};
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}
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/* I2C master won't acknowledge the last byte read from the
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* slave device. Divide the read command in two segments as
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* recommended by the ESP32 Technical Reference Manual.
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*/
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if (msg.len - to_read <= 1U) {
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/* Read the last byte and explicitly ask for an
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* acknowledgment.
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*/
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*cmd++ = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_READ,
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.num_bytes = 1,
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.ack_val = true,
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};
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/* Account for the `msg.len - 1` when clamping
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* transmission length to FIFO buffer size.
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*/
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to_read++;
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if (msg.flags & I2C_MSG_STOP) {
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wait_cmd = cmd;
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*cmd++ = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_STOP
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};
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}
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}
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if (!wait_cmd) {
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*cmd++ = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_END
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};
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}
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ret = i2c_esp32_transmit_wait(dev, wait_cmd);
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if (ret < 0) {
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return ret;
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}
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for (i = 0U; i < to_read; i++) {
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u32_t v = sys_read32(I2C_DATA_APB_REG(config->index));
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*msg.buf++ = v & I2C_FIFO_RDATA;
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}
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msg.len -= to_read;
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i2c_esp32_reset_fifo(config);
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}
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return 0;
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}
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static int i2c_esp32_write_msg(struct device *dev, u16_t addr,
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struct i2c_msg msg)
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{
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const struct i2c_esp32_config *config = dev->config->config_info;
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volatile struct i2c_esp32_cmd *cmd =
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(void *)I2C_COMD0_REG(config->index);
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*cmd++ = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_RSTART
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};
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cmd = i2c_esp32_write_addr(dev, cmd, &msg, addr);
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for (; msg.len; cmd = (void *)I2C_COMD0_REG(config->index)) {
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u32_t to_send = MIN(I2C_ESP32_BUFFER_SIZE, msg.len);
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u32_t i;
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int ret;
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/* Copy data to TX fifo */
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for (i = 0U; i < to_send; i++) {
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sys_write32(*msg.buf++,
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I2C_DATA_APB_REG(config->index));
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}
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*cmd++ = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_WRITE,
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.num_bytes = to_send,
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.ack_en = true,
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};
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msg.len -= to_send;
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if (!msg.len && (msg.flags & I2C_MSG_STOP)) {
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*cmd = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_STOP
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};
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} else {
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*cmd = (struct i2c_esp32_cmd) {
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.opcode = I2C_ESP32_OP_END
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};
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}
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ret = i2c_esp32_transmit_wait(dev, cmd);
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if (ret < 0) {
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return ret;
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}
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i2c_esp32_reset_fifo(config);
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}
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|
return 0;
|
|
}
|
|
|
|
static int i2c_esp32_transfer(struct device *dev, struct i2c_msg *msgs,
|
|
u8_t num_msgs, u16_t addr)
|
|
{
|
|
struct i2c_esp32_data *data = dev->driver_data;
|
|
int ret = 0;
|
|
u8_t i;
|
|
|
|
k_sem_take(&data->transfer_sem, K_FOREVER);
|
|
|
|
/* Mask out unused address bits, and make room for R/W bit */
|
|
addr &= BIT_MASK(data->dev_config & I2C_ADDR_10_BITS ? 10 : 7);
|
|
addr <<= 1;
|
|
|
|
for (i = 0U; i < num_msgs; i++) {
|
|
if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
|
|
ret = i2c_esp32_write_msg(dev, addr, msgs[i]);
|
|
} else {
|
|
ret = i2c_esp32_read_msg(dev, addr, msgs[i]);
|
|
}
|
|
|
|
if (ret < 0) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
k_sem_give(&data->transfer_sem);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void i2c_esp32_isr(void *arg)
|
|
{
|
|
const int fifo_give_mask = I2C_ACK_ERR_INT_ST |
|
|
I2C_TIME_OUT_INT_ST |
|
|
I2C_TRANS_COMPLETE_INT_ST |
|
|
I2C_ARBITRATION_LOST_INT_ST;
|
|
struct device *device = arg;
|
|
const struct i2c_esp32_config *config = device->config->config_info;
|
|
|
|
if (sys_read32(I2C_INT_STATUS_REG(config->index)) & fifo_give_mask) {
|
|
struct i2c_esp32_data *data = device->driver_data;
|
|
|
|
/* Only give the semaphore if a watched interrupt happens.
|
|
* Error checking is performed at the other side of the
|
|
* semaphore, by reading the status register.
|
|
*/
|
|
k_sem_give(&data->fifo_sem);
|
|
}
|
|
|
|
/* Acknowledge all I2C interrupts */
|
|
sys_write32(~0, I2C_INT_CLR_REG(config->index));
|
|
}
|
|
|
|
static int i2c_esp32_init(struct device *dev);
|
|
|
|
static const struct i2c_driver_api i2c_esp32_driver_api = {
|
|
.configure = i2c_esp32_configure,
|
|
.transfer = i2c_esp32_transfer,
|
|
};
|
|
|
|
#ifdef CONFIG_I2C_0
|
|
DEVICE_DECLARE(i2c_esp32_0);
|
|
|
|
static void i2c_esp32_connect_irq_0(void)
|
|
{
|
|
IRQ_CONNECT(CONFIG_I2C_ESP32_0_IRQ, 1, i2c_esp32_isr,
|
|
DEVICE_GET(i2c_esp32_0), 0);
|
|
}
|
|
|
|
static const struct i2c_esp32_config i2c_esp32_config_0 = {
|
|
.index = 0,
|
|
.connect_irq = i2c_esp32_connect_irq_0,
|
|
.sig = {
|
|
.sda_out = I2CEXT0_SDA_OUT_IDX,
|
|
.sda_in = I2CEXT0_SDA_IN_IDX,
|
|
.scl_out = I2CEXT0_SCL_OUT_IDX,
|
|
.scl_in = I2CEXT0_SCL_IN_IDX,
|
|
},
|
|
.pins = {
|
|
.scl = CONFIG_I2C_ESP32_0_SCL_PIN,
|
|
.sda = CONFIG_I2C_ESP32_0_SDA_PIN,
|
|
},
|
|
.peripheral = {
|
|
.clk = DPORT_I2C_EXT0_CLK_EN,
|
|
.rst = DPORT_I2C_EXT0_RST,
|
|
},
|
|
.mode = {
|
|
.tx_lsb_first =
|
|
IS_ENABLED(CONFIG_I2C_ESP32_0_TX_LSB_FIRST),
|
|
.rx_lsb_first =
|
|
IS_ENABLED(CONFIG_I2C_ESP32_0_RX_LSB_FIRST),
|
|
},
|
|
.irq = {
|
|
.source = ETS_I2C_EXT0_INTR_SOURCE,
|
|
.line = CONFIG_I2C_ESP32_0_IRQ,
|
|
},
|
|
.default_config = CONFIG_I2C_0_DEFAULT_CFG,
|
|
};
|
|
|
|
static struct i2c_esp32_data i2c_esp32_data_0;
|
|
|
|
DEVICE_AND_API_INIT(i2c_esp32_0, CONFIG_I2C_0_NAME, &i2c_esp32_init,
|
|
&i2c_esp32_data_0, &i2c_esp32_config_0,
|
|
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
|
|
&i2c_esp32_driver_api);
|
|
#endif /* CONFIG_I2C_0 */
|
|
|
|
#ifdef CONFIG_I2C_1
|
|
DEVICE_DECLARE(i2c_esp32_1);
|
|
|
|
static void i2c_esp32_connect_irq_1(void)
|
|
{
|
|
IRQ_CONNECT(CONFIG_I2C_ESP32_1_IRQ, 1, i2c_esp32_isr,
|
|
DEVICE_GET(i2c_esp32_1), 0);
|
|
}
|
|
|
|
static const struct i2c_esp32_config i2c_esp32_config_1 = {
|
|
.index = 1,
|
|
.connect_irq = i2c_esp32_connect_irq_1,
|
|
.sig = {
|
|
.sda_out = I2CEXT1_SDA_OUT_IDX,
|
|
.sda_in = I2CEXT1_SDA_IN_IDX,
|
|
.scl_out = I2CEXT1_SCL_OUT_IDX,
|
|
.scl_in = I2CEXT1_SCL_IN_IDX,
|
|
},
|
|
.pins = {
|
|
.scl = CONFIG_I2C_ESP32_1_SCL_PIN,
|
|
.sda = CONFIG_I2C_ESP32_1_SDA_PIN,
|
|
},
|
|
.peripheral = {
|
|
.clk = DPORT_I2C_EXT1_CLK_EN,
|
|
.rst = DPORT_I2C_EXT1_RST,
|
|
},
|
|
.mode = {
|
|
.tx_lsb_first =
|
|
IS_ENABLED(CONFIG_I2C_ESP32_1_TX_LSB_FIRST),
|
|
.rx_lsb_first =
|
|
IS_ENABLED(CONFIG_I2C_ESP32_1_RX_LSB_FIRST),
|
|
},
|
|
.irq = {
|
|
.source = ETS_I2C_EXT1_INTR_SOURCE,
|
|
.line = CONFIG_I2C_ESP32_1_IRQ,
|
|
},
|
|
.default_config = CONFIG_I2C_1_DEFAULT_CFG,
|
|
};
|
|
|
|
static struct i2c_esp32_data i2c_esp32_data_1;
|
|
|
|
DEVICE_AND_API_INIT(i2c_esp32_1, CONFIG_I2C_1_NAME, &i2c_esp32_init,
|
|
&i2c_esp32_data_1, &i2c_esp32_config_1,
|
|
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
|
|
&i2c_esp32_driver_api);
|
|
#endif /* CONFIG_I2C_1 */
|
|
|
|
static int i2c_esp32_init(struct device *dev)
|
|
{
|
|
const struct i2c_esp32_config *config = dev->config->config_info;
|
|
struct i2c_esp32_data *data = dev->driver_data;
|
|
unsigned int key = irq_lock();
|
|
|
|
k_sem_init(&data->fifo_sem, 1, 1);
|
|
k_sem_init(&data->transfer_sem, 1, 1);
|
|
|
|
irq_disable(config->irq.line);
|
|
|
|
/* Even if irq_enable() is called on config->irq.line, disable
|
|
* interrupt sources in the I2C controller.
|
|
*/
|
|
sys_write32(0, I2C_INT_ENA_REG(config->index));
|
|
esp32_rom_intr_matrix_set(0, config->irq.source, config->irq.line);
|
|
|
|
config->connect_irq();
|
|
irq_unlock(key);
|
|
|
|
return i2c_esp32_configure(dev, config->default_config);
|
|
}
|