Leandro Pereira 4d5fbbc517 arch: arm: Flush pipeline after switching privilege levels ... During the transition of privilege levels while performing syscalls, the ARM documentation recommends flushing the pipeline to avoid pre-fetched instructions from being executed with the previous privilege level. The manual says: 4.16 CONTROL register (...) after programming the CONTROL register, an ISB instruction should be used. (...) This is not implemented in the Cortex M0 processor. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>		2018-04-13 15:35:45 -05:00
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arc	arch/quark_se_c1000_ss: Switch to SPI DW driver	2018-04-04 19:02:35 +02:00
arm	arch: arm: Flush pipeline after switching privilege levels	2018-04-13 15:35:45 -05:00
common	drivers/interrupt_controller: Introduce multi-level interrupt support	2018-02-06 22:39:05 -05:00
nios2	cleanup: replace old jira numbers with GH issues	2018-03-26 13:13:04 -04:00
posix	kernel: POSIX: Compatibility layer for POSIX message queue APIs.	2018-04-03 15:30:44 -04:00
riscv32	arch: riscv32: fe310: Always-On domain adress definition	2018-04-05 08:08:08 -05:00
x86	arch/quark_se: Enable SPI port 2 as a slave only	2018-04-04 19:02:35 +02:00
xtensa	xtensa, kernel/sched: Move next switch_handle selection to the scheduler	2018-03-18 16:58:12 -04:00
CMakeLists.txt	…
Kconfig	arch: arc: Use DTS for all ARC SoCs	2018-03-23 10:13:53 +01:00