109 lines
2.1 KiB
Plaintext
109 lines
2.1 KiB
Plaintext
#include <arm/armv6-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-m0+";
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reg = <0>;
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};
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};
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "FLASH_0";
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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};
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soc {
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usart0: usart@4000c000 { /* USART0 */
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compatible = "silabs,gecko-usart";
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reg = <0x4000c000 0x400>;
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interrupts = <17 0>, <18 0>;
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interrupt-names = "rx", "tx";
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status = "disabled";
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label = "UART_0";
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};
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usart1: usart@4000c400 { /* USART1 */
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compatible = "silabs,gecko-usart";
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reg = <0x4000c400 0x400>;
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interrupts = <8 0>, <9 0>;
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interrupt-names = "rx", "tx";
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status = "disabled";
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label = "UART_1";
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};
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gpio@40006100 {
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compatible = "silabs,efm32-gpio";
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reg = <0x40006100 0xf00>;
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interrupts = <1 0 6 0>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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label = "GPIO";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@40006000 {
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compatible = "silabs,efm32-gpio-port";
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reg = <0x40006000 0x24>;
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label = "GPIO_A";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiob: gpio@40006024 {
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compatible = "silabs,efm32-gpio-port";
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reg = <0x40006024 0x24>;
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label = "GPIO_B";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioc: gpio@40006048 {
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compatible = "silabs,efm32-gpio-port";
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reg = <0x40006048 0x24>;
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label = "GPIO_C";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiod: gpio@4000606c {
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compatible = "silabs,efm32-gpio-port";
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reg = <0x4000606c 0x24>;
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label = "GPIO_D";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioe: gpio@40006090 {
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compatible = "silabs,efm32-gpio-port";
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reg = <0x40006090 0x24>;
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label = "GPIO_E";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpiof: gpio@400060b4 {
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compatible = "silabs,efm32-gpio-port";
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reg = <0x400060b4 0x24>;
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label = "GPIO_F";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};
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