149 lines
4.2 KiB
Plaintext
149 lines
4.2 KiB
Plaintext
# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
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# SPDX-License-Identifier: Apache-2.0
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config RISCV_ISA_RV32I
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bool
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help
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RV32I Base Integer Instruction Set - 32bit
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config RISCV_ISA_RV32E
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bool
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help
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RV32E Base Integer Instruction Set (Embedded) - 32bit
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config RISCV_ISA_RV64I
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bool
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default y if 64BIT
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help
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RV64I Base Integer Instruction Set - 64bit
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config RISCV_ISA_RV128I
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bool
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help
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RV128I Base Integer Instruction Set - 128bit
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config RISCV_ISA_EXT_M
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bool
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help
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(M) - Standard Extension for Integer Multiplication and Division
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Standard integer multiplication and division instruction extension,
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which is named "M" and contains instructions that multiply or divide
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values held in two integer registers.
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config RISCV_ISA_EXT_A
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bool
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help
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(A) - Standard Extension for Atomic Instructions
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The standard atomic instruction extension is denoted by instruction
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subset name "A", and contains instructions that atomically
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read-modify-write memory to support synchronization between multiple
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RISC-V threads running in the same memory space.
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config RISCV_ISA_EXT_F
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bool
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help
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(F) - Standard Extension for Single-Precision Floating-Point
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Standard instruction-set extension for single-precision
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floating-point, which is named "F" and adds single-precision
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floating-point computational instructions compliant with the IEEE
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754-2008 arithmetic standard.
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config RISCV_ISA_EXT_D
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bool
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depends on RISCV_ISA_EXT_F
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help
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(D) - Standard Extension for Double-Precision Floating-Point
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Standard double-precision floating-point instruction-set extension,
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which is named "D" and adds double-precision floating-point
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computational instructions compliant with the IEEE 754-2008
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arithmetic standard.
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config RISCV_ISA_EXT_G
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bool
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_F
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select RISCV_ISA_EXT_D
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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help
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(IMAFDZicsr_Zifencei) IMAFDZicsr_Zifencei extensions
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config RISCV_ISA_EXT_Q
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bool
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depends on RISCV_ISA_RV64I
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depends on RISCV_ISA_EXT_F
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depends on RISCV_ISA_EXT_D
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help
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(Q) - Standard Extension for Quad-Precision Floating-Point
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Standard extension for 128-bit binary floating-point instructions
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compliant with the IEEE 754-2008 arithmetic standard. The 128-bit or
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quad-precision binary floatingpoint instruction subset is named "Q".
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config RISCV_ISA_EXT_C
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bool
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help
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(C) - Standard Extension for Compressed Instructions
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RISC-V standard compressed instruction set extension, named "C",
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which reduces static and dynamic code size by adding short 16-bit
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instruction encodings for common operations.
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config RISCV_ISA_EXT_ZICSR
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bool
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help
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(Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions
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The "Zicsr" extension introduces support for the full set of CSR
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instructions that operate on CSRs registers.
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config RISCV_ISA_EXT_ZIFENCEI
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bool
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help
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(Zifencei) - Standard Extension for Instruction-Fetch Fence
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The "Zifencei" extension includes the FENCE.I instruction that
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provides explicit synchronization between writes to instruction
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memory and instruction fetches on the same hart.
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config RISCV_ISA_EXT_ZBA
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bool
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help
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(Zba) - Zba BitManip Extension
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The Zba instructions can be used to accelerate the generation of
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addresses that index into arrays of basic types (halfword, word,
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doubleword) using both unsigned word-sized and XLEN-sized indices: a
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shifted index is added to a base address.
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config RISCV_ISA_EXT_ZBB
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bool
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help
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(Zbb) - Zbb BitManip Extension (Basic bit-manipulation)
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The Zbb instructions can be used for basic bit-manipulation (logical
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with negate, count leading / trailing zero bits, count population,
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etc...).
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config RISCV_ISA_EXT_ZBC
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bool
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help
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(Zbc) - Zbc BitManip Extension (Carry-less multiplication)
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The Zbc instructions can be used for carry-less multiplication that
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is the multiplication in the polynomial ring over GF(2).
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config RISCV_ISA_EXT_ZBS
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bool
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help
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(Zbs) - Zbs BitManip Extension (Single-bit instructions)
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The Zbs instructions can be used for single-bit instructions that
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provide a mechanism to set, clear, invert, or extract a single bit in
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a register.
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