zephyr/dts/arm/st/f4/stm32f401.dtsi

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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f4.dtsi>
/ {
soc {
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
spi4: spi@40013400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <84 5>;
status = "disabled";
label = "SPI_4";
};
i2s2: i2s@40003800 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
dmas = <&dma1 4 0 0x400 0x3
&dma1 3 0 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_2";
};
i2s3: i2s@40003c00 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
dmas = <&dma1 5 0 0x400 0x3
&dma1 0 0 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_3";
};
};
};