69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation.
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* Copyright (c) 2021 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/pm/state.h>
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#include <zephyr/toolchain.h>
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BUILD_ASSERT(DT_NODE_EXISTS(DT_PATH(cpus)),
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"cpus node not defined in Devicetree");
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/**
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* Check CPU power state consistency.
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*
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* @param i Power state index.
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* @param node_id CPU node identifier.
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*/
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#define CHECK_POWER_STATE_CONSISTENCY(i, node_id) \
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BUILD_ASSERT( \
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DT_PROP_BY_PHANDLE_IDX_OR(node_id, cpu_power_states, i, \
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min_residency_us, 0U) >= \
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DT_PROP_BY_PHANDLE_IDX_OR(node_id, cpu_power_states, i, \
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exit_latency_us, 0U), \
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"Found CPU power state with min_residency < exit_latency")
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/**
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* @brief Check CPU power states consistency
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*
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* All states should have a minimum residency >= than the exit latency.
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*
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* @param node_id A CPU node identifier.
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*/
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#define CHECK_POWER_STATES_CONSISTENCY(node_id) \
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LISTIFY(DT_PROP_LEN_OR(node_id, cpu_power_states, 0), \
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CHECK_POWER_STATE_CONSISTENCY, (;), node_id); \
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/* Check that all power states are consistent */
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DT_FOREACH_CHILD(DT_PATH(cpus), CHECK_POWER_STATES_CONSISTENCY)
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#define DEFINE_CPU_STATES(n) \
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static const struct pm_state_info pmstates_##n[] \
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= PM_STATE_INFO_LIST_FROM_DT_CPU(n);
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#define CPU_STATE_REF(n) pmstates_##n
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DT_FOREACH_CHILD(DT_PATH(cpus), DEFINE_CPU_STATES);
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/** CPU power states information for each CPU */
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static const struct pm_state_info *cpus_states[] = {
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DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), CPU_STATE_REF, (,))
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};
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/** Number of states for each CPU */
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static const uint8_t states_per_cpu[] = {
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DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), DT_NUM_CPU_POWER_STATES, (,))
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};
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uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states)
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{
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if (cpu >= ARRAY_SIZE(cpus_states)) {
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return 0;
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}
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*states = cpus_states[cpu];
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return states_per_cpu[cpu];
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}
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