113 lines
3.8 KiB
C
113 lines
3.8 KiB
C
/*
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* pinmux_board_quark_d2000_crb.c - Quark D2000 Customer Reference
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* Board pinmux driver
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*/
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file pinmux operations for Quark_D2000
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*/
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#include <nanokernel.h>
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#include <board.h>
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#include <device.h>
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#include <init.h>
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#include <pinmux.h>
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#include <sys_io.h>
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#include "pinmux/pinmux.h"
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#include "pinmux_quark_mcu.h"
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/***************************
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* PINMUX mapping
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*
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* The following lines detail the possible options for the pinmux and their
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* associated pins and ball points.
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* This is the full pinmap that we have available on the board for configuration
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* including the ball position and the various modes that can be set. In the
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* _pinmux_defaults we do not spend any time setting values that are using mode
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* A as the hardware brings up all devices by default in mode A.
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*/
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/* pin, ball, mode A, mode B, mode C */
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/* 0 F00, gpio_0, ai_0, spi_m_ss0 */
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/* 1 F01, gpio_1, ai_1, spi_m_ss1 */
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/* 2 F02, gpio_2, ai_2, spi_m_ss2 */
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/* 3 F03, gpio_3, ai_3, spi_m_ss3 */
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/* 4 F04, gpio_4, ai_4, rtc_clk_out */
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/* 5 F05, gpio_5, ai_5, sys_clk_out */
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/* 6 F06, gpio_6, ai_6, i2c_scl */
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/* 7 F07, gpio_7, ai_7, i2c_sda */
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/* 8 F08, gpio_8, ai_8, spi_s_sclk */
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/* 9 F09, gpio_9, ai_9, spi_s_sdin */
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/* 10 F10, gpio_10, ai_10, spi_s_sdout */
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/* 11 F11, gpio_11, ai_11, spi_s_scs */
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/* 12 F12, gpio_12, ai_12, uart_a_txd */
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/* 13 F13, gpio_13, ai_13, uart_a_rxd */
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/* 14 F14, gpio_14, ai_14, uart_a_rts */
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/* 15 F15, gpio_15, ai_15, uart_a_cts */
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/* 16 F16, gpio_16, ai_16, spi_m_sclk */
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/* 17 F17, gpio_17, ai_17, spi_m_mosi */
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/* 18 F18, gpio_18, ai_18, spi_m_miso */
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/* 19 F19, tdo, gpio_19, pwm0 */
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/* 20 F20, trst_n, gpio_20, uart_b_txd */
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/* 21 F21, tck, gpio_21, uart_b_rxd */
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/* 22 F22, tms, gpio_22, uart_b_rts */
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/* 23 F23, tdi, gpio_23, uart_b_cts */
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/* 24 F24, gpio_24, lpd_sig_out, pwm1 */
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/******** End PINMUX mapping **************************/
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#define PINMUX_MAX_REGISTERS 2
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static void _pinmux_defaults(uint32_t base)
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{
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uint32_t mux_config[PINMUX_MAX_REGISTERS] = { 0, 0 };
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int i = 0;
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PIN_CONFIG(mux_config, 0, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 3, PINMUX_FUNC_B);
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PIN_CONFIG(mux_config, 4, PINMUX_FUNC_B);
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PIN_CONFIG(mux_config, 6, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 7, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 12, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 13, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 14, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 15, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 16, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 17, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 18, PINMUX_FUNC_C);
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for (i = 0; i < PINMUX_MAX_REGISTERS; i++) {
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sys_write32(mux_config[i], PINMUX_SELECT_REGISTER(base, i));
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}
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}
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static int pinmux_initialize(struct device *port)
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{
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ARG_UNUSED(port);
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_pinmux_defaults(PINMUX_BASE_ADDR);
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/* Enable the UART RX pin to receive input */
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_quark_mcu_set_mux(PINMUX_BASE_ADDR + PINMUX_INPUT_OFFSET, 5, 0x1);
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return 0;
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}
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SYS_INIT(pinmux_initialize, SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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