335 lines
8.7 KiB
C
335 lines
8.7 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __DAI_PARAMS_INTEL_IPC4_H__
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#define __DAI_PARAMS_INTEL_IPC4_H__
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#include <stdint.h>
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#define DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT 8
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/**< Type of the gateway. */
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enum dai_intel_ipc4_connector_node_id_type {
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/**< HD/A host output (-> DSP). */
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dai_intel_ipc4_hda_host_output_class = 0,
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/**< HD/A host input (<- DSP). */
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dai_intel_ipc4_hda_host_input_class = 1,
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/**< HD/A host input/output (rsvd for future use). */
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dai_intel_ipc4_hda_host_inout_class = 2,
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/**< HD/A link output (DSP ->). */
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dai_intel_ipc4_hda_link_output_class = 8,
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/**< HD/A link input (DSP <-). */
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dai_intel_ipc4_hda_link_input_class = 9,
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/**< HD/A link input/output (rsvd for future use). */
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dai_intel_ipc4_hda_link_inout_class = 10,
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/**< DMIC link input (DSP <-). */
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dai_intel_ipc4_dmic_link_input_class = 11,
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/**< I2S link output (DSP ->). */
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dai_intel_ipc4_i2s_link_output_class = 12,
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/**< I2S link input (DSP <-). */
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dai_intel_ipc4_i2s_link_input_class = 13,
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/**< ALH link output, legacy for SNDW (DSP ->). */
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dai_intel_ipc4_alh_link_output_class = 16,
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/**< ALH link input, legacy for SNDW (DSP <-). */
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dai_intel_ipc4_alh_link_input_class = 17,
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/**< SNDW link output (DSP ->). */
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dai_intel_ipc4_alh_snd_wire_stream_link_output_class = 16,
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/**< SNDW link input (DSP <-). */
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dai_intel_ipc4_alh_snd_wire_stream_link_input_class = 17,
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/**< UAOL link output (DSP ->). */
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dai_intel_ipc4_alh_uaol_stream_link_output_class = 18,
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/**< UAOL link input (DSP <-). */
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dai_intel_ipc4_alh_uaol_stream_link_input_class = 19,
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/**< IPC output (DSP ->). */
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dai_intel_ipc4_ipc_output_class = 20,
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/**< IPC input (DSP <-). */
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dai_intel_ipc4_ipc_input_class = 21,
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/**< I2S Multi gtw output (DSP ->). */
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dai_intel_ipc4_i2s_multi_link_output_class = 22,
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/**< I2S Multi gtw input (DSP <-). */
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dai_intel_ipc4_i2s_multi_link_input_class = 23,
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/**< GPIO */
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dai_intel_ipc4_gpio_class = 24,
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/**< SPI */
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dai_intel_ipc4_spi_output_class = 25,
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dai_intel_ipc4_spi_input_class = 26,
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dai_intel_ipc4_max_connector_node_id_type
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};
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struct ssp_intel_aux_tlv {
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uint32_t type;
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uint32_t size;
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uint32_t val[];
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} __packed;
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struct ssp_intel_mn_ctl {
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uint32_t div_m;
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uint32_t div_n;
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} __packed;
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struct ssp_intel_clk_ctl {
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uint32_t start;
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uint32_t stop;
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} __packed;
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struct ssp_intel_tr_ctl {
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uint32_t sampling_frequency;
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uint32_t bit_depth;
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uint32_t channel_map;
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uint32_t channel_config;
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uint32_t interleaving_style;
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uint32_t format;
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} __packed;
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struct ssp_intel_run_ctl {
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uint32_t enabled;
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} __packed;
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struct ssp_intel_node_ctl {
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uint32_t node_id;
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uint32_t sampling_rate;
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} __packed;
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struct ssp_intel_sync_ctl {
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uint32_t sync_denominator;
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uint32_t count;
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} __packed;
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struct ssp_intel_ext_ctl {
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uint32_t ext_data;
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} __packed;
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struct ssp_intel_link_ctl {
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uint32_t clock_source;
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} __packed;
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#define SSP_MN_DIVIDER_CONTROLS 0
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#define SSP_DMA_CLK_CONTROLS 1
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#define SSP_DMA_TRANSMISSION_START 2
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#define SSP_DMA_TRANSMISSION_STOP 3
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#define SSP_DMA_ALWAYS_RUNNING_MODE 4
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#define SSP_DMA_SYNC_DATA 5
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#define SSP_DMA_CLK_CONTROLS_EXT 6
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#define SSP_LINK_CLK_SOURCE 7
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/**< Base top-level structure of an address of a gateway. */
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/*!
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* The virtual index value, presented on the top level as raw 8 bits,
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* is expected to be encoded in a gateway specific way depending on
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* the actual type of gateway.
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*/
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union dai_intel_ipc4_connector_node_id {
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/**< Raw 32-bit value of node id. */
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uint32_t dw;
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/**< Bit fields */
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struct {
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/**< Index of the virtual DMA at the gateway. */
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uint32_t v_index : 8;
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/**< Type of the gateway, one of ConnectorNodeId::Type values. */
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uint32_t dma_type : 5;
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/**< Rsvd field. */
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uint32_t _rsvd : 19;
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} f; /**<< Bits */
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} __packed;
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/*!
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* Attributes are usually provided along with the gateway configuration
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* BLOB when the FW is requested to instantiate that gateway.
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*
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* There are flags which requests FW to allocate gateway related data
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* (buffers and other items used while transferring data, like linked list)
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* to be allocated from a special memory area, e.g low power memory.
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*/
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union dai_intel_ipc4_gateway_attributes {
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/**< Raw value */
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uint32_t dw;
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/**< Access to the fields */
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struct {
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/**< Gateway data requested in low power memory. */
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uint32_t lp_buffer_alloc : 1;
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/**< Gateway data requested in register file memory. */
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uint32_t alloc_from_reg_file : 1;
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/**< Reserved field */
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uint32_t _rsvd : 30;
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} bits; /**<< Bits */
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} __packed;
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/**< Configuration for the IPC Gateway */
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struct dai_intel_ipc4_gateway_config_blob {
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/**< Size of the gateway buffer, specified in bytes */
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uint32_t buffer_size;
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/**< Flags */
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union flags {
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struct bits {
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/**< Activates high threshold notification */
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/*!
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* Indicates whether notification should be sent to the host
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* when the size of data in the buffer reaches the high threshold
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* specified by threshold_high parameter.
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*/
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uint32_t notif_high : 1;
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/**< Activates low threshold notification */
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/*!
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* Indicates whether notification should be sent to the host
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* when the size of data in the buffer reaches the low threshold
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* specified by threshold_low parameter.
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*/
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uint32_t notif_low : 1;
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/**< Reserved field */
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uint32_t rsvd : 30;
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} f; /**<< Bits */
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/**< Raw value of flags */
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uint32_t flags_raw;
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} u; /**<< Flags */
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/**< High threshold */
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/*!
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* Specifies the high threshold (in bytes) for notifying the host
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* about the buffered data level.
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*/
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uint32_t threshold_high;
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/**< Low threshold */
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/*!
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* Specifies the low threshold (in bytes) for notifying the host
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* about the buffered data level.
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*/
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uint32_t threshold_low;
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} __packed;
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/* i2s Configuration BLOB building blocks */
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/* i2s registers for i2s Configuration */
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struct dai_intel_ipc4_ssp_config {
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uint32_t ssc0;
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uint32_t ssc1;
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uint32_t sscto;
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uint32_t sspsp;
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uint32_t sstsa;
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uint32_t ssrsa;
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uint32_t ssc2;
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uint32_t sspsp2;
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uint32_t ssc3;
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uint32_t ssioc;
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} __packed;
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struct dai_intel_ipc4_ssp_mclk_config {
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/* master clock divider control register */
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uint32_t mdivc;
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/* master clock divider ratio register */
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uint32_t mdivr;
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} __packed;
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struct dai_intel_ipc4_ssp_mclk_config_2 {
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uint32_t mdivctlr;
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uint32_t mdivrcnt;
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uint32_t mdivr[];
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} __packed;
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struct dai_intel_ipc4_ssp_driver_config {
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struct dai_intel_ipc4_ssp_config i2s_config;
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struct dai_intel_ipc4_ssp_mclk_config mclk_config;
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} __packed;
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struct dai_intel_ipc4_ssp_start_control {
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/* delay in msec between enabling interface (moment when
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* Copier instance is being attached to the interface) and actual
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* interface start. Value of 0 means no delay.
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*/
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uint32_t clock_warm_up : 16;
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/* specifies if parameters target MCLK (1) or SCLK (0) */
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uint32_t mclk : 1;
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/* value of 1 means that clock should be started immediately
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* even if no Copier instance is currently attached to the interface.
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*/
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uint32_t warm_up_ovr : 1;
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uint32_t rsvd0 : 14;
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} __packed;
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struct dai_intel_ipc4_ssp_stop_control {
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/* delay in msec between stopping the interface
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* (moment when Copier instance is being detached from the interface)
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* and interface clock stop. Value of 0 means no delay.
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*/
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uint32_t clock_stop_delay : 16;
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/* value of 1 means that clock should be kept running (infinite
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* stop delay) after Copier instance detaches from the interface.
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*/
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uint32_t keep_running : 1;
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/* value of 1 means that clock should be stopped immediately */
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uint32_t clock_stop_ovr : 1;
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uint32_t rsvd1 : 14;
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} __packed;
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union dai_intel_ipc4_ssp_dma_control {
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struct dai_intel_ipc4_ssp_control {
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struct dai_intel_ipc4_ssp_start_control start_control;
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struct dai_intel_ipc4_ssp_stop_control stop_control;
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} control_data;
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struct dai_intel_ipc4_mn_div_config {
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uint32_t mval;
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uint32_t nval;
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} mndiv_control_data;
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} __packed;
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struct dai_intel_ipc4_ssp_configuration_blob {
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union dai_intel_ipc4_gateway_attributes gw_attr;
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/* TDM time slot mappings */
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uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT];
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/* i2s port configuration */
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struct dai_intel_ipc4_ssp_driver_config i2s_driver_config;
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/* optional configuration parameters */
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union dai_intel_ipc4_ssp_dma_control i2s_dma_control[0];
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} __packed;
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#define SSP_BLOB_VER_1_5 0xee000105
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struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 {
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union dai_intel_ipc4_gateway_attributes gw_attr;
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uint32_t version;
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uint32_t size;
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/* TDM time slot mappings */
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uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT];
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/* i2s port configuration */
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struct dai_intel_ipc4_ssp_config i2s_ssp_config;
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/* clock configuration parameters */
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struct dai_intel_ipc4_ssp_mclk_config_2 i2s_mclk_control;
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} __packed;
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#endif
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