zephyr/soc/xtensa/intel_s1000
Ulf Magnusson 984bfae831 global: Remove leading/trailing blank lines in files
Remove leading/trailing blank lines in .c, .h, .py, .rst, .yml, and
.yaml files.

Will avoid failures with the new CI test in
https://github.com/zephyrproject-rtos/ci-tools/pull/112, though it only
checks changed files.

Move the 'target-notes' target in boards/xtensa/odroid_go/doc/index.rst
to get rid of the trailing blank line there. It was probably misplaced.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-12-11 19:17:27 +01:00
..
include global: Remove leading/trailing blank lines in files 2019-12-11 19:17:27 +01:00
CMakeLists.txt soc: intel_s1000_crb: fix XCC build error with newlib 2019-12-02 09:58:00 -05:00
Kconfig.defconfig kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
Kconfig.soc soc: intel_s1000_crb: fix cmake warning about HAS_*_DW 2019-12-02 09:58:00 -05:00
dts_fixup.h soc: intel_s1000_crb: update LP_SRAM macros 2019-11-13 06:26:10 -06:00
iomux.h
linker.ld soc: intel_s1000: define default MEMCTL reg value 2019-11-13 06:26:10 -06:00
memory.h
soc.c soc: xtensa/intel_s1000_crb: fix build error on xtensa_api.h 2019-11-07 21:34:03 -05:00
soc.h intel_s1000: implement z_soc_irq_is_enabled() 2019-09-07 10:20:51 -04:00
xcc_newlib_fix.c soc: intel_s1000_crb: fix XCC build error with newlib 2019-12-02 09:58:00 -05:00