81 lines
3.0 KiB
C
81 lines
3.0 KiB
C
/*
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/* SRAM0 (64k), SRAM1 (416k), SRAM2 (64k) memories
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* Ibus and Dbus address space
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*/
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#define SRAM0_IRAM_START 0x40370000
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#define SRAM0_SIZE 0x8000
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#define SRAM1_DRAM_START 0x3fc88000
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/* IRAM equivalent address where DRAM actually start */
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#define SRAM1_IRAM_START (SRAM0_IRAM_START + SRAM0_SIZE)
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#define SRAM2_DRAM_START 0x3fcf0000
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#define SRAM2_SIZE 0x10000
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/** Simplified memory map for the bootloader.
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* Make sure the bootloader can load into main memory without overwriting itself.
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*
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* ESP32-S3 ROM static data usage is as follows:
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* - 0x3fcd7e00 - 0x3fce9704: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x3fce9710 - 0x3fceb710: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fceb710 - 0x3fced710: APP CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fced710 - 0x3fcf0000: ROM .bss and .data (not easily reclaimable)
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*
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* The 2nd stage bootloader can take space up to the end of ROM shared
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* buffers area (0x3fce9704). For alignment purpose we shall use value (0x3fce9700).
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*/
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/* The offset between Dbus and Ibus.
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* Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses.
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*/
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#define IRAM_DRAM_OFFSET 0x6f0000
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#define DRAM_BUFFERS_START 0x3fcd7e00
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#define DRAM_PROCPU_STACK_START 0x3fce9710
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#define DRAM_STACK_START DRAM_PROCPU_STACK_START
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#define DRAM_APPCPU_STACK_START 0x3fceb710
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#define DRAM_ROM_BSS_DATA_START 0x3fcf0000
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/* Base address used for calculating memory layout
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* counted from Dbus backwards and back to the Ibus
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*/
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#define BOOTLOADER_USABLE_DRAM_END DRAM_BUFFERS_START
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/* For safety margin between bootloader data section and startup stacks */
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#define BOOTLOADER_STACK_OVERHEAD 0x0
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#define BOOTLOADER_DRAM_SEG_LEN 0x6600
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#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x2c00
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#define BOOTLOADER_IRAM_SEG_LEN 0x9000
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/* Start of the lower region is determined by region size and the end of the higher region */
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#define BOOTLOADER_DRAM_SEG_END (BOOTLOADER_USABLE_DRAM_END - BOOTLOADER_STACK_OVERHEAD)
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#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_DRAM_SEG_END - BOOTLOADER_DRAM_SEG_LEN)
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#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_DRAM_SEG_START - \
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BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET)
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#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN)
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/* Flash */
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#ifdef CONFIG_FLASH_SIZE
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#define FLASH_SIZE CONFIG_FLASH_SIZE
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#else
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#define FLASH_SIZE 0x800000
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#endif
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/* Cached memory */
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#define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE
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#define IROM_SEG_ORG 0x42000000
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#define IROM_SEG_LEN FLASH_SIZE
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#define DROM_SEG_ORG 0x3c000000
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#define DROM_SEG_LEN FLASH_SIZE
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/* AMP */
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#ifdef CONFIG_SOC_ENABLE_APPCPU
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#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM
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#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM
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#else
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#define APPCPU_IRAM_SIZE 0
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#define APPCPU_DRAM_SIZE 0
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#endif
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