103 lines
3.4 KiB
C
103 lines
3.4 KiB
C
/*
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* Copyright (c) 2017 Google LLC.
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* Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com>
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* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_ATMEL_SAM0_SAMR21_SOC_H_
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#define _SOC_ATMEL_SAM0_SAMR21_SOC_H_
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#ifndef _ASMLANGUAGE
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#define DONT_USE_CMSIS_INIT
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#include <zephyr/types.h>
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#if defined(CONFIG_SOC_SAMR21E16A)
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#include <samr21e16a.h>
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#elif defined(CONFIG_SOC_SAMR21E17A)
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#include <samr21e17a.h>
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#elif defined(CONFIG_SOC_SAMR21E18A)
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#include <samr21e18a.h>
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#elif defined(CONFIG_SOC_SAMR21E19A)
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#include <samr21e19a.h>
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#elif defined(CONFIG_SOC_SAMR21G16A)
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#include <samr21g16a.h>
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#elif defined(CONFIG_SOC_SAMR21G17A)
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#include <samr21g17a.h>
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#elif defined(CONFIG_SOC_SAMR21G18A)
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#include <samr21g18a.h>
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#else
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#error Library does not support the specified device.
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#endif
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#endif /* _ASMLANGUAGE */
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#include "adc_fixup_sam0.h"
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#include "../common/soc_port.h"
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#include "../common/atmel_sam0_dt.h"
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/** Processor Clock (HCLK) Frequency */
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#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ
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/** Master Clock (MCK) Frequency */
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#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
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/** Known values */
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#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000
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#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768
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#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768
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#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000
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#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768
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#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250
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/** GCLK1 source frequency selector */
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#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ
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#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ
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#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ
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#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
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#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ
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#else
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#error Unsupported GCLK1 clock source.
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#endif
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/** Dividers and frequency for GCLK0 */
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#define SOC_ATMEL_SAM0_GCLK0_DIV \
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(SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ)
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#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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/** DFLL48M output frequency */
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#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \
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(SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV)
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/** Dividers and frequency for GCLK1 */
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#define SOC_ATMEL_SAM0_GCLK1_DIV \
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(SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ)
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#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \
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(SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV)
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/** DFLL48M output multiplier */
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#define SOC_ATMEL_SAM0_DFLL48M_MUL \
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(SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ)
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/** Frequency for GCLK2 */
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#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ
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/** Dividers and frequency for GCLK3 */
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#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
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#define SOC_ATMEL_SAM0_GCLK3_DIV \
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(SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ)
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#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#endif /* _SOC_ATMEL_SAM0_SAMR21_SOC_H_ */
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