148 lines
5.4 KiB
C
148 lines
5.4 KiB
C
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the pulpino core
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*/
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#ifndef __PULPINO_SOC_H_
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#define __PULPINO_SOC_H_
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/* CSR Registers */
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#define PULP_MESTATUS 0x7C0 /* Machine Exception Status Register */
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#define PULP_LPSTART0 0x7B0 /* Hardware Loop 0 Start Register */
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#define PULP_LPEND0 0x7B1 /* Hardware Loop 0 End Register */
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#define PULP_LPCOUNT0 0x7B2 /* Hardware Loop 0 Count Register */
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#define PULP_LPSTART1 0x7B4 /* Hardware Loop 1 Start Register */
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#define PULP_LPEND1 0x7B5 /* Hardware Loop 1 End Register */
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#define PULP_LPCOUNT1 0x7B6 /* Hardware Loop 1 Count Register */
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/* IRQ numbers */
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#define PULP_I2C_0_IRQ 23 /* I2C Controller */
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#define PULP_UART_0_IRQ 24 /* Uart Controller */
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#define PULP_GPIO_0_IRQ 25 /* GPIO Controller */
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#define PULP_SPI_0_IRQ 26 /* SPI Controller #0 */
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#define PULP_SPI_1_IRQ 27 /* SPI Controller #1 */
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#define PULP_TIMER_A_OVERFLOW_IRQ 28 /* Timer Overflow A */
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#define PULP_TIMER_A_CMP_IRQ 29 /* Timer Output Cmp A */
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#define PULP_TIMER_B_OVERFLOW_IRQ 30 /* Timer Overflow B */
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#define PULP_TIMER_B_CMP_IRQ 31 /* Timer Output Cmp B */
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/* min value to consider as IRQ in MCAUSE register */
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#define PULP_MIN_IRQ PULP_I2C_0_IRQ
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/* Exception numbers */
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#define PULP_ECALL_EXP 11 /* ECALL Instruction */
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/*
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* SOC-specific MSTATUS related info
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*/
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/* MSTATUS register to save/restore upon interrupt/exception/context switch */
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#define SOC_MSTATUS_REG PULP_MESTATUS
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#define SOC_MSTATUS_IEN (1 << 0) /* Machine Interrupt Enable bit */
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/*
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* Default MSTATUS register value to restore from stack
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* upon scheduling a thread for the first time
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*/
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#define SOC_MSTATUS_DEF_RESTORE SOC_MSTATUS_IEN
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/* SOC-specific MCAUSE bitfields */
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#define SOC_MCAUSE_EXP_MASK 0x1F /* Exception code Mask */
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#define SOC_MCAUSE_ECALL_EXP PULP_ECALL_EXP /* ECALL exception number */
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/* SOC-Specific EXIT ISR command */
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#define SOC_ERET eret
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/* UART configuration */
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#define UART_NS16550_PORT_0_BASE_ADDR 0x1A100000
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#define UART_NS16550_PORT_0_CLK_FREQ 2500000
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#define UART_NS16550_PORT_0_IRQ PULP_UART_0_IRQ
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/* GPIO configuration */
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#define PULP_GPIO_0_BASE 0x1A101000
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/* PAD configuration */
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#define PULP_PAD_BASE 0x1A107000
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/* IRQ configuration */
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#define PULP_IRQ_BASE 0x1A104000
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#define PULP_IER_ADDR (PULP_IRQ_BASE + 0x00) /* IRQ Enable Register */
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#define PULP_IPR_ADDR (PULP_IRQ_BASE + 0x04) /* IRQ Pending Register */
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#define PULP_ISP_ADDR (PULP_IRQ_BASE + 0x08) /* IRQ Set Pending Register */
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#define PULP_ICP_ADDR (PULP_IRQ_BASE + 0x0C) /* IRQ Clear Pending Register */
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#define PULP_EER_ADDR (PULP_IRQ_BASE + 0x10) /* Event Enable Register */
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#define PULP_EPR_ADDR (PULP_IRQ_BASE + 0x14) /* Event Pending Register */
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#define PULP_ESP_ADDR (PULP_IRQ_BASE + 0x18) /* Event Set Pending Register */
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#define PULP_ECP_ADDR (PULP_IRQ_BASE + 0x1C) /* Event Clear Pending Register */
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#define PULP_SCR_ADDR (PULP_IRQ_BASE + 0x20) /* Sleep Control Register */
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/* Timer configuration */
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#define PULP_TIMER_A_BASE 0x1A103000
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#define PULP_TIMER_B_BASE 0x1A103010
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/*
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* Zephyr-SDK makes use a the latest generic riscv32 toolchain, which
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* encodes the wfi opcode as 0x10500073. Pulpino does not understand
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* this opcode and will generate a fault upon execution. Pulpino core
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* implementation is based on a previous RISC-V ISA specification and
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* expects the wfi opcode to be encoded as 0x10200073. In new toolchain,
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* 0x10200073 opcode is used to represent the sret opcode. Hence,
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* when compiled with a generic riscv32 toolchain, define wfi by sret
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* in assembly code.
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*/
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#if defined(CONFIG_RISCV_GENERIC_TOOLCHAIN)
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#define wfi sret
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#endif
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#ifndef _ASMLANGUAGE
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#include <irq.h>
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/* Register Access MACRO */
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#define PULP_REG(x) (*((volatile unsigned int *)(x)))
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/* Interrupt Registers */
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#define PULP_IER PULP_REG(PULP_IER_ADDR)
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#define PULP_IPR PULP_REG(PULP_IPR_ADDR)
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#define PULP_ISP PULP_REG(PULP_ISP_ADDR)
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#define PULP_ICP PULP_REG(PULP_ICP_ADDR)
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#define PULP_EER PULP_REG(PULP_EER_ADDR)
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#define PULP_EPR PULP_REG(PULP_EPR_ADDR)
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#define PULP_ESP PULP_REG(PULP_ESP_ADDR)
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#define PULP_ECP PULP_REG(PULP_ECP_ADDR)
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#define PULP_SCR PULP_REG(PULP_SCR_ADDR)
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/* PAD MUX register */
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#define PULP_PADMUX PULP_REG(PULP_PAD_BASE)
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#define PULP_PAD_SPI 0
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#define PULP_PAD_GPIO 1
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#define PULP_PAD_MASK 1
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
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void soc_interrupt_init(void);
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#endif
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/*
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* when a generic riscv32 toolchain is used replaced wfi by sret
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* in inline assembly. Explanation given above.
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*/
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#if defined(CONFIG_RISCV_GENERIC_TOOLCHAIN)
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#define SOC_WFI __asm__ volatile("sret")
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#else
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#define SOC_WFI __asm__ volatile("wfi")
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#endif
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/* lib-c hooks required RAM defined variables */
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#define RISCV_RAM_BASE CONFIG_DTCM_BASE_ADDRESS
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#define RISCV_RAM_SIZE CONFIG_DTCM_SIZE
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#endif /* !_ASMLANGUAGE */
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#endif /* __PULPINO_SOC_H_ */
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