83 lines
2.4 KiB
C
83 lines
2.4 KiB
C
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief RISCV32 kernel structure member offset definition file
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*
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* This module is responsible for the generation of the absolute symbols whose
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* value represents the member offsets for various RISCV32 kernel
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* structures.
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*/
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#include <gen_offset.h>
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#include <kernel_structs.h>
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#include <kernel_offsets.h>
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/* thread_arch_t member offsets */
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GEN_OFFSET_SYM(_thread_arch_t, swap_return_value);
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/* struct coop member offsets */
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GEN_OFFSET_SYM(_callee_saved_t, sp);
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GEN_OFFSET_SYM(_callee_saved_t, s0);
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GEN_OFFSET_SYM(_callee_saved_t, s1);
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GEN_OFFSET_SYM(_callee_saved_t, s2);
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GEN_OFFSET_SYM(_callee_saved_t, s3);
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GEN_OFFSET_SYM(_callee_saved_t, s4);
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GEN_OFFSET_SYM(_callee_saved_t, s5);
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GEN_OFFSET_SYM(_callee_saved_t, s6);
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GEN_OFFSET_SYM(_callee_saved_t, s7);
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GEN_OFFSET_SYM(_callee_saved_t, s8);
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GEN_OFFSET_SYM(_callee_saved_t, s9);
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GEN_OFFSET_SYM(_callee_saved_t, s10);
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GEN_OFFSET_SYM(_callee_saved_t, s11);
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/* esf member offsets */
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GEN_OFFSET_SYM(NANO_ESF, ra);
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GEN_OFFSET_SYM(NANO_ESF, gp);
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GEN_OFFSET_SYM(NANO_ESF, tp);
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GEN_OFFSET_SYM(NANO_ESF, t0);
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GEN_OFFSET_SYM(NANO_ESF, t1);
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GEN_OFFSET_SYM(NANO_ESF, t2);
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GEN_OFFSET_SYM(NANO_ESF, t3);
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GEN_OFFSET_SYM(NANO_ESF, t4);
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GEN_OFFSET_SYM(NANO_ESF, t5);
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GEN_OFFSET_SYM(NANO_ESF, t6);
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GEN_OFFSET_SYM(NANO_ESF, a0);
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GEN_OFFSET_SYM(NANO_ESF, a1);
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GEN_OFFSET_SYM(NANO_ESF, a2);
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GEN_OFFSET_SYM(NANO_ESF, a3);
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GEN_OFFSET_SYM(NANO_ESF, a4);
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GEN_OFFSET_SYM(NANO_ESF, a5);
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GEN_OFFSET_SYM(NANO_ESF, a6);
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GEN_OFFSET_SYM(NANO_ESF, a7);
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GEN_OFFSET_SYM(NANO_ESF, mepc);
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GEN_OFFSET_SYM(NANO_ESF, mstatus);
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#if defined(CONFIG_SOC_RISCV32_PULPINO)
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GEN_OFFSET_SYM(NANO_ESF, lpstart0);
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GEN_OFFSET_SYM(NANO_ESF, lpend0);
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GEN_OFFSET_SYM(NANO_ESF, lpcount0);
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GEN_OFFSET_SYM(NANO_ESF, lpstart1);
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GEN_OFFSET_SYM(NANO_ESF, lpend1);
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GEN_OFFSET_SYM(NANO_ESF, lpcount1);
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#endif
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/*
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* RISC-V requires the stack to be 16-bytes aligned, hence SP needs to grow or
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* shrink by a size, which follows the RISC-V stack alignment requirements
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* Hence, ensure that __tTCS_NOFLOAT_SIZEOF and __tTCS_NOFLOAT_SIZEOF sizes
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* are aligned accordingly.
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*/
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GEN_ABSOLUTE_SYM(__NANO_ESF_SIZEOF, STACK_ROUND_UP(sizeof(NANO_ESF)));
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/* size of the struct tcs structure sans save area for floating point regs */
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GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF,
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STACK_ROUND_UP(sizeof(struct k_thread)));
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GEN_ABS_SYM_END
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