82 lines
2.0 KiB
Plaintext
82 lines
2.0 KiB
Plaintext
# XTENSA architecture configuration options
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "XTENSA Options"
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depends on XTENSA
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menu "Specific core configuration"
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config IRQ_OFFLOAD_INTNUM
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int "IRQ offload SW interrupt index"
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help
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The index of the software interrupt to be used for IRQ offload.
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Please note that in order for IRQ offload to work correctly the selected
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interrupt shall have its priority shall not exceed XCHAL_EXCM_LEVEL.
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endmenu
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config ARCH
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default "xtensa"
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config SIMULATOR_XTENSA
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bool "Simulator Configuration"
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help
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Specify if the board configuration should be treated as a simulator.
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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prompt "Hardware clock cycles per second, 2000000 for ISS"
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default 2000000
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range 1000000 1000000000
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help
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This option specifies hardware clock.
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config XTENSA_NO_IPC
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bool "Core has no IPC support"
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select ATOMIC_OPERATIONS_C
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help
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Uncheck this if you core does not implement "SCOMPARE1" register and "s32c1i"
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instruction.
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config XTENSA_RESET_VECTOR
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bool "Build reset vector code"
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default y
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help
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This option controls whether the initial reset vector code is built.
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This is always needed for the simulator. Real boards may already
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implement this in boot ROM.
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if XTENSA_RESET_VECTOR
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config RESET_VECTOR_IN_BOOTLOADER
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bool "Link reset vector into bootloader"
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default n
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help
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Reset vector code can be either linked in the bootloader or the
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application binary. Select "y" to link it into the bootloader.
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endif
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config XTENSA_USE_CORE_CRT1
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bool "Use crt1.S from core"
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default y
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help
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SoC or boards might define their own __start by setting this setting
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to false.
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config XTENSA_KERNEL_CPU_PTR_SR
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string
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default "MISC0"
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help
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Specify which special register to store the pointer to
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_kernel.cpus[] for the current CPU.
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config XTENSA_ENABLE_BACKTRACE
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bool "Enable backtrace on panic exception"
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default y
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depends on SOC_ESP32
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help
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Enable this config option to print backtrace on panic exception
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endmenu
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