277 lines
7.0 KiB
C
277 lines
7.0 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @brief Driver for Reset & Clock Control of STM32F10x family processor.
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*
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* Based on reference manual:
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* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 7: Low-, medium-, high- and XL-density reset and
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* clock control
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*/
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#include <soc.h>
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#include <soc_registers.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <clock_control/stm32_clock_control.h>
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struct stm32f10x_rcc_data {
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uint8_t *base;
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};
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static inline int stm32f10x_clock_control_on(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32f10x_rcc_data *data = dev->driver_data;
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volatile struct stm32f10x_rcc *rcc = (struct stm32f10x_rcc *)(data->base);
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uint32_t subsys = POINTER_TO_UINT(sub_system);
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if (subsys > STM32F10X_CLOCK_APB2_BASE) {
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subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
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rcc->apb2enr |= subsys;
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} else {
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rcc->apb1enr |= subsys;
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}
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return 0;
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}
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static inline int stm32f10x_clock_control_off(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32f10x_rcc_data *data = dev->driver_data;
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volatile struct stm32f10x_rcc *rcc =
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(struct stm32f10x_rcc *)(data->base);
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uint32_t subsys = POINTER_TO_UINT(sub_system);
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if (subsys > STM32F10X_CLOCK_APB2_BASE) {
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subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
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rcc->apb2enr &= ~subsys;
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} else {
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rcc->apb1enr &= ~subsys;
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}
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return 0;
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}
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/**
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* @brief helper for mapping a setting to register value
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*/
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struct regval_map {
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int val;
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int reg;
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};
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int map_reg_val(const struct regval_map *map, size_t cnt, int val)
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{
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for (int i = 0; i < cnt; i++) {
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if (map[i].val == val) {
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return map[i].reg;
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}
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}
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return 0;
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}
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/**
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* @brief map APB prescaler setting to register value
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*/
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static int __apb_prescaler(int prescaler)
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{
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if (prescaler == 0) {
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return STM32F10X_RCC_CFG_HCLK_DIV_0;
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}
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const struct regval_map map[] = {
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{0, STM32F10X_RCC_CFG_HCLK_DIV_0},
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{2, STM32F10X_RCC_CFG_HCLK_DIV_2},
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{4, STM32F10X_RCC_CFG_HCLK_DIV_4},
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{8, STM32F10X_RCC_CFG_HCLK_DIV_8},
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{16, STM32F10X_RCC_CFG_HCLK_DIV_16},
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};
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return map_reg_val(map, ARRAY_SIZE(map), prescaler);
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}
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/**
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* @brief map AHB prescaler setting to register value
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*/
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static int __ahb_prescaler(int prescaler)
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{
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if (prescaler == 0)
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return STM32F10X_RCC_CFG_SYSCLK_DIV_0;
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const struct regval_map map[] = {
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{0, STM32F10X_RCC_CFG_SYSCLK_DIV_0},
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{2, STM32F10X_RCC_CFG_SYSCLK_DIV_2},
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{4, STM32F10X_RCC_CFG_SYSCLK_DIV_4},
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{8, STM32F10X_RCC_CFG_SYSCLK_DIV_8},
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{16, STM32F10X_RCC_CFG_SYSCLK_DIV_16},
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{64, STM32F10X_RCC_CFG_SYSCLK_DIV_64},
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{128, STM32F10X_RCC_CFG_SYSCLK_DIV_128},
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{256, STM32F10X_RCC_CFG_SYSCLK_DIV_256},
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{512, STM32F10X_RCC_CFG_SYSCLK_DIV_512},
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};
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return map_reg_val(map, ARRAY_SIZE(map), prescaler);
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}
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/**
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* @brief map PLL multiplier setting to register value
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*/
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static int __pllmul(int mul)
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{
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/* x2 -> 0x0
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* x3 -> 0x1
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* x4 -> 0x2
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* ...
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* x15 -> 0xd
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* x16 -> 0xe
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* x16 -> 0xf
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*/
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return mul - 2;
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}
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uint32_t __get_ahb_clock(uint32_t sysclk)
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{
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/* AHB clock is generated based on SYSCLK */
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uint32_t sysclk_div = CONFIG_CLOCK_STM32F10X_AHB_PRESCALER;
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if (sysclk_div == 0) {
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sysclk_div = 1;
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}
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return sysclk / sysclk_div;
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}
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uint32_t __get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
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{
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if (prescaler == 0) {
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prescaler = 1;
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}
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return ahb_clock / prescaler;
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}
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static int stm32f10x_clock_control_get_subsys_rate(struct device *clock,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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ARG_UNUSED(clock);
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uint32_t subsys = POINTER_TO_UINT(sub_system);
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uint32_t prescaler = CONFIG_CLOCK_STM32F10X_APB1_PRESCALER;
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if (subsys > STM32F10X_CLOCK_APB2_BASE) {
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prescaler = CONFIG_CLOCK_STM32F10X_APB2_PRESCALER;
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}
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/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
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uint32_t ahb_clock =
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__get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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*rate = __get_apb_clock(ahb_clock, prescaler);
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return 0;
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}
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static struct clock_control_driver_api stm32f10x_clock_control_api = {
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.on = stm32f10x_clock_control_on,
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.off = stm32f10x_clock_control_off,
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.get_rate = stm32f10x_clock_control_get_subsys_rate,
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};
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int stm32f10x_clock_control_init(struct device *dev)
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{
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struct stm32f10x_rcc_data *data = dev->driver_data;
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volatile struct stm32f10x_rcc *rcc =
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(struct stm32f10x_rcc *)(data->base);
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/* enable HSI clock */
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rcc->cr.bit.hsion = 1;
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/* this should end after one test */
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while (rcc->cr.bit.hsirdy != 1) {
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}
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/* disable PLL */
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rcc->cr.bit.pllon = 0;
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#ifdef CONFIG_CLOCK_STM32F10X_PLL_SRC_HSI
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/* PLL input from HSI/2 = 4MHz */
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rcc->cfgr.bit.pllsrc = STM32F10X_RCC_CFG_PLL_SRC_HSI;
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#elif defined(CONFIG_CLOCK_STM32F10X_PLL_SRC_PREDIV1)
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#error PREDIV1 as PLL source is not supported
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rcc->cfgr.bit.pllsrc = STM32F10X_RCC_CFG_PLL_SRC_PREDIV1;
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#endif
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uint32_t pllmul = __pllmul(CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER);
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/* setup PLL multiplication (PLL must be disabled) */
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rcc->cfgr.bit.pllmul = pllmul;
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/* enable PLL */
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rcc->cr.bit.pllon = 1;
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/* wait for PLL to become ready */
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while (rcc->cr.bit.pllrdy != 1) {
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}
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uint32_t hpre = __ahb_prescaler(CONFIG_CLOCK_STM32F10X_AHB_PRESCALER);
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/* setup AHB prescaler */
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rcc->cfgr.bit.hpre = hpre;
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uint32_t ppre1 = __apb_prescaler(CONFIG_CLOCK_STM32F10X_APB1_PRESCALER);
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/* setup APB1, must not exceed 36MHz, prescaler set to 0 */
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rcc->cfgr.bit.ppre1 = ppre1;
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uint32_t ppre2 = __apb_prescaler(CONFIG_CLOCK_STM32F10X_APB2_PRESCALER);
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/* setup APB2 to use 36MHz, prescaler set to 0 */
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rcc->cfgr.bit.ppre2 = ppre2;
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/* setup SYSCLK source, default to HSI */
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int sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSI;
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#ifdef CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_PLL
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sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_PLL;
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#elif defined(CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_HSE)
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sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSE;
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#endif
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/* set SYSCLK clock value */
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rcc->cfgr.bit.sw = sysclk_src;
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/* wait for SYSCLK to switch the source */
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while (rcc->cfgr.bit.sws != sysclk_src) {
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}
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dev->driver_api = &stm32f10x_clock_control_api;
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return 0;
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}
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static struct stm32f10x_rcc_data stm32f10x_rcc_data = {
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.base = (uint8_t *)RCC_BASE,
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};
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/* FIXME: move prescaler/multiplier defines into device config */
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/**
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* @brief RCC device, note that priority is intentionally set to 1 so
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* that the device init runs just after SOC init
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*/
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DEVICE_INIT(rcc_stm32f10x, STM32_CLOCK_CONTROL_NAME,
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&stm32f10x_clock_control_init,
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&stm32f10x_rcc_data, NULL,
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PRIMARY, CONFIG_CLOCK_CONTROL_STM32F10X_DEVICE_PRIORITY);
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