88 lines
2.1 KiB
C
88 lines
2.1 KiB
C
/*
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* Copyright (c) 2021 STMicroelectronics.
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* Copyright (c) 2021 G-Technologies Sdn. Bhd.
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* Copyright (c) 2022 Worldcoin Foundation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/pm/pm.h>
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#include <soc.h>
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#include <clock_control/clock_stm32_ll_common.h>
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#include <stm32g4xx_ll_bus.h>
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#include <stm32g4xx_ll_cortex.h>
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#include <stm32g4xx_ll_pwr.h>
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#include <stm32g4xx_ll_system.h>
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#include <stm32g4xx_ll_utils.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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/* Invoke Low Power/System Off specific Tasks */
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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if (state != PM_STATE_SUSPEND_TO_IDLE) {
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LOG_DBG("Unsupported power state %u", state);
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return;
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}
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switch (substate_id) {
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case 1: /* this corresponds to the STOP0 mode: */
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/* enter STOP0 mode */
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LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0);
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LL_LPM_EnableDeepSleep();
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/* enter SLEEP mode : WFE or WFI */
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k_cpu_idle();
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break;
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case 2: /* this corresponds to the STOP1 mode: */
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/* enter STOP1 mode */
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LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
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LL_LPM_EnableDeepSleep();
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/* enter SLEEP mode : WFE or WFI */
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k_cpu_idle();
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break;
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default:
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LOG_DBG("Unsupported power state substate-id %u", substate_id);
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break;
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}
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}
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/* Handle SOC specific activity after Low Power Mode Exit */
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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if (state != PM_STATE_SUSPEND_TO_IDLE) {
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LOG_DBG("Unsupported power substate %u", state);
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} else {
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switch (substate_id) {
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case 1: /* STOP0 */
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__fallthrough;
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case 2: /* STOP1 */
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LL_LPM_DisableSleepOnExit();
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/* Clear SLEEPDEEP bit */
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LL_LPM_EnableSleep();
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break;
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default:
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LOG_DBG("Unsupported power substate-id %u", substate_id);
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break;
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}
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/* need to restore the clock */
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stm32_clock_control_init(NULL);
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}
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/*
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* System is now in active mode.
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* Reenable interrupts which were disabled
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* when OS started idling code.
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*/
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irq_unlock(0);
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}
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/* Initialize STM32 Power */
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void stm32_power_init(void)
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{
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/* enable Power clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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}
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