170 lines
5.3 KiB
C
170 lines
5.3 KiB
C
/*
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* Copyright 2021, 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
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#define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
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#define PLATFORM_CORE_COUNT 1
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/** Id of master DSP core */
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#define PLATFORM_PRIMARY_CORE_ID 0
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#define IRAM_RESERVE_HEADER_SPACE 0x400
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#define IRAM_BASE 0x3B6F8000
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#define IRAM_SIZE 0x800
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#define SDRAM0_BASE 0x92400000
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#define SDRAM0_SIZE 0x800000
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#define SDRAM1_BASE 0x92C00000
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#define SDRAM1_SIZE 0x800000
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/* The reset vector address in SRAM and its size */
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#define MEM_RESET_TEXT_SIZE 0x2E0
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#define MEM_RESET_LIT_SIZE 0x120
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/* This is the base address of all the vectors defined in IRAM */
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#define XCHAL_VECBASE_RESET_PADDR_IRAM \
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(IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
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#define MEM_VECBASE_LIT_SIZE 0x178
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/*
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* EXCEPTIONS and VECTORS
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*/
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#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x3B6F8000
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/* Vector and literal sizes */
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#define MEM_VECT_LIT_SIZE 0x4
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#define MEM_VECT_TEXT_SIZE 0x1C
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#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\
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MEM_VECT_LIT_SIZE)
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/* The addresses of the vectors.
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* Only the mem_error vector continues to point to its ROM address.
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*/
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#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \
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(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
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#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \
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(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
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#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \
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(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
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#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \
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(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
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#define XCHAL_KERNEL_VECTOR_PADDR_IRAM \
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(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
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#define XCHAL_USER_VECTOR_PADDR_IRAM \
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(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
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#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \
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(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
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/* Location for the intList section which is later used to construct the
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* Interrupt Descriptor Table (IDT). This is a bogus address as this
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* section will be stripped off in the final image.
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*/
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#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
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/* size of the Interrupt Descriptor Table (IDT) */
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#define IDT_SIZE 0x2000
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/* physical DSP addresses */
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#define IRAM_BASE 0x3B6F8000
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#define IRAM_SIZE 0x800
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#define DRAM0_BASE 0x3B6E8000
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#define DRAM0_SIZE 0x8000
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#define DRAM1_BASE 0x3B6F0000
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#define DRAM1_SIZE 0x8000
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#define SDRAM0_BASE 0x92400000
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#define SDRAM0_SIZE 0x800000
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#define SDRAM1_BASE 0x92C00000
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#define SDRAM1_SIZE 0x800000
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#define XSHAL_MU2_SIDEB_BYPASS_PADDR 0x30E70000
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#define MU_BASE XSHAL_MU2_SIDEB_BYPASS_PADDR
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#define SDMA2_BASE 0x30E10000
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#define SDMA2_SIZE 0x10000
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#define SDMA3_BASE 0x30E00000
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#define SDMA3_SIZE 0x10000
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#define SAI_1_BASE 0x30C10000
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#define SAI_1_SIZE 0x00010000
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#define SAI_3_BASE 0x30C30000
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#define SAI_3_SIZE 0x00010000
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#define UUID_ENTRY_ELF_BASE 0x1FFFA000
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#define UUID_ENTRY_ELF_SIZE 0x6000
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#define LOG_ENTRY_ELF_BASE 0x20000000
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#define LOG_ENTRY_ELF_SIZE 0x2000000
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#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
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#define EXT_MANIFEST_ELF_SIZE 0x2000000
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/*
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* The Heap and Stack on i.MX8 are organized like this :-
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*
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* +--------------------------------------------------------------------------+
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* | Offset | Region | Size |
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* +---------------------+----------------+-----------------------------------+
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* | SDRAM_BASE | RO Data | SOF_DATA_SIZE |
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* | | Data | |
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* | | BSS | |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | SOF_STACK_END | Stack | SOF_STACK_SIZE |
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* +---------------------+----------------+-----------------------------------+
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* | SOF_STACK_BASE | | |
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* +---------------------+----------------+-----------------------------------+
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*/
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#define SRAM_OUTBOX_BASE SDRAM1_BASE
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#define SRAM_OUTBOX_SIZE 0x1000
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#define SRAM_OUTBOX_OFFSET 0
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#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
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#define SRAM_INBOX_SIZE 0x1000
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#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE
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#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
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#define SRAM_DEBUG_SIZE 0x800
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#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
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#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
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#define SRAM_EXCEPT_SIZE 0x800
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#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
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#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
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#define SRAM_STREAM_SIZE 0x1000
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#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
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#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
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#define SRAM_TRACE_SIZE 0x1000
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#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
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#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
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+ SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
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+ SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
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#endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */
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