111 lines
2.5 KiB
Plaintext
111 lines
2.5 KiB
Plaintext
# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_MIMX8MM6_A53
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select ARM64
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select CPU_CORTEX_A53
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select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
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select HAS_MCUX if CLOCK_CONTROL
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select HAS_MCUX_CCM if CLOCK_CONTROL
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select HAS_MCUX_IOMUXC if PINCTRL
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select HAS_MCUX_RDC
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select HAS_MCUX_CACHE
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select SOC_PREP_HOOK
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config SOC_MIMX8MM6_M4
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select ARM
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select CPU_CORTEX_M4
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select HAS_MCUX
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select HAS_MCUX_CCM
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select HAS_MCUX_RDC
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select HAS_MCUX_IGPIO
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select HAS_MCUX_IOMUXC
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select SOC_EARLY_INIT_HOOK
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config SOC_MIMX8ML8_A53
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select ARM64
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select CPU_CORTEX_A53
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select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
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select HAS_MCUX if CLOCK_CONTROL
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select HAS_MCUX_CCM if CLOCK_CONTROL
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select HAS_MCUX_IOMUXC if PINCTRL
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select HAS_MCUX_RDC
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select HAS_MCUX_CACHE
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select SOC_PREP_HOOK
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config SOC_MIMX8MN6_A53
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select ARM64
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select CPU_CORTEX_A53
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select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
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select HAS_MCUX if CLOCK_CONTROL
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select HAS_MCUX_CCM if CLOCK_CONTROL
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select HAS_MCUX_IOMUXC if PINCTRL
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select HAS_MCUX_RDC
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select HAS_MCUX_CACHE
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select SOC_PREP_HOOK
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config SOC_MIMX8ML8_ADSP
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select XTENSA
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select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
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select XTENSA_RESET_VECTOR
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select XTENSA_USE_CORE_CRT1
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select ATOMIC_OPERATIONS_BUILTIN
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select GEN_ISR_TABLES
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select XTENSA_SMALL_VECTOR_TABLE_ENTRY
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select HAS_MCUX if CLOCK_CONTROL
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select HAS_MCUX_CCM if CLOCK_CONTROL
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select HAS_MCUX_IOMUXC if PINCTRL
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select PINCTRL_IMX if HAS_MCUX_IOMUXC
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select CPU_HAS_DCACHE
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config SOC_MIMX8ML8_M7
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select ARM
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select CPU_CORTEX_M7
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select CPU_HAS_FPU
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select CPU_HAS_ICACHE
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select CPU_HAS_DCACHE
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select INIT_VIDEO_PLL
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select HAS_MCUX
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select HAS_MCUX_CCM
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select HAS_MCUX_RDC
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select CPU_HAS_ARM_MPU
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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select ARM_MPU
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select HAS_MCUX_IGPIO
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select HAS_MCUX_IOMUXC
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select SOC_EARLY_INIT_HOOK
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config SOC_MIMX8MQ6_M4
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select ARM
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select CPU_CORTEX_M4
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select HAS_MCUX
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select HAS_MCUX_CCM
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select HAS_MCUX_RDC
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select HAS_MCUX_IOMUXC
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config MCUX_CORE_SUFFIX
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default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53
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default "_dsp" if SOC_MIMX8ML8_ADSP
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if SOC_MIMX8ML8_M7
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choice CODE_LOCATION
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prompt "Code location selection"
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config CODE_ITCM
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bool "Link code into internal instruction tightly coupled memory (ITCM)"
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config CODE_DDR
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bool "Link code into DDR memory"
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endchoice
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config INIT_VIDEO_PLL
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bool "Initialize Video PLL"
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endif # SOC_MIMX8ML8_M7
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