58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _NUVOTON_NPCX_SOC_H_
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#define _NUVOTON_NPCX_SOC_H_
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#include <cmsis_core_m_defaults.h>
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/* NPCX9 SCFG multi-registers */
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#define NPCX_DEVALT_OFFSET(n) (0x010 + n)
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#define NPCX_PUPD_EN_OFFSET(n) (0x028 + n)
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#define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n))
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#define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n)
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/* NPCX9 MIWU multi-registers */
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#define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010))
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#define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010))
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#define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010))
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#define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010))
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#define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010))
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#define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010))
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#define NPCX_WKST_OFFSET(n) (0x006 + (n * 0x010))
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#define NPCX_WKINEN_OFFSET(n) (0x007 + (n * 0x010))
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/* NPCX9 ADC multi-registers */
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#define NPCX_CHNDAT_OFFSET(n) (0x040 + (n * 2))
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#define NPCX_THRCTL_OFFSET(n) (0x060 + (n * 2))
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/* NPCX9 ADC register fields */
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#define NPCX_THRCTL_THEN 15
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#define NPCX_THRCTL_L_H 14
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#define NPCX_THRCTL_CHNSEL FIELD(10, 4)
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#define NPCX_THRCTL_THRVAL FIELD(0, 10)
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/* NPCX9 FIU register fields */
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#define NPCX_FIU_EXT_CFG_SPI1_2DEV 7
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/* NPCX9 supported group mask of DEVALT_LK */
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#define NPCX_DEVALT_LK_GROUP_MASK \
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(BIT(0) | BIT(2) | BIT(3) | BIT(4) | \
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BIT(5) | BIT(6) | BIT(11) | BIT(13) | \
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BIT(15) | BIT(16) | BIT(17) | BIT(18)) /* DEVALT0_LK - DEVALTJ_LK */
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/* NPCX9 Clock configuration and limitation */
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#define MAX_OFMCLK 100000000
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#include <reg/reg_access.h>
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#include <reg/reg_def.h>
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#include <soc_dt.h>
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#include <soc_clock.h>
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#include <soc_pins.h>
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#include <soc_power.h>
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#endif /* _NUVOTON_NPCX_SOC_H_ */
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