214 lines
7.0 KiB
C
214 lines
7.0 KiB
C
/*
|
|
* Copyright (c) 2021 Bosch Sensortec GmbH
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#ifndef ZEPHYR_DRIVERS_SENSOR_BMI270_BMI270_H_
|
|
#define ZEPHYR_DRIVERS_SENSOR_BMI270_BMI270_H_
|
|
|
|
#include <zephyr/device.h>
|
|
#include <zephyr/sys/util.h>
|
|
#include <zephyr/types.h>
|
|
#include <zephyr/drivers/sensor.h>
|
|
#include <zephyr/drivers/i2c.h>
|
|
|
|
#define BMI270_REG_CHIP_ID 0x00
|
|
#define BMI270_REG_ERROR 0x02
|
|
#define BMI270_REG_STATUS 0x03
|
|
#define BMI270_REG_AUX_X_LSB 0x04
|
|
#define BMI270_REG_ACC_X_LSB 0x0C
|
|
#define BMI270_REG_GYR_X_LSB 0x12
|
|
#define BMI270_REG_SENSORTIME_0 0x18
|
|
#define BMI270_REG_EVENT 0x1B
|
|
#define BMI270_REG_INT_STATUS_0 0x1C
|
|
#define BMI270_REG_SC_OUT_0 0x1E
|
|
#define BMI270_REG_WR_GEST_ACT 0x20
|
|
#define BMI270_REG_INTERNAL_STATUS 0x21
|
|
#define BMI270_REG_TEMPERATURE_0 0x22
|
|
#define BMI270_REG_FIFO_LENGTH_0 0x24
|
|
#define BMI270_REG_FIFO_DATA 0x26
|
|
#define BMI270_REG_FEAT_PAGE 0x2F
|
|
#define BMI270_REG_FEATURES_0 0x30
|
|
#define BMI270_REG_ACC_CONF 0x40
|
|
#define BMI270_REG_ACC_RANGE 0x41
|
|
#define BMI270_REG_GYR_CONF 0x42
|
|
#define BMI270_REG_GYR_RANGE 0x43
|
|
#define BMI270_REG_AUX_CONF 0x44
|
|
#define BMI270_REG_FIFO_DOWNS 0x45
|
|
#define BMI270_REG_FIFO_WTM_0 0x46
|
|
#define BMI270_REG_FIFO_CONFIG_0 0x48
|
|
#define BMI270_REG_SATURATION 0x4A
|
|
#define BMI270_REG_AUX_DEV_ID 0x4B
|
|
#define BMI270_REG_AUX_IF_CONF 0x4C
|
|
#define BMI270_REG_AUX_RD_ADDR 0x4D
|
|
#define BMI270_REG_AUX_WR_ADDR 0x4E
|
|
#define BMI270_REG_AUX_WR_DATA 0x4F
|
|
#define BMI270_REG_ERR_REG_MSK 0x52
|
|
#define BMI270_REG_INT1_IO_CTRL 0x53
|
|
#define BMI270_REG_INT2_IO_CTRL 0x54
|
|
#define BMI270_REG_INT_LATCH 0x55
|
|
#define BMI270_REG_INT1_MAP_FEAT 0x56
|
|
#define BMI270_REG_INT2_MAP_FEAT 0x57
|
|
#define BMI270_REG_INT_MAP_DATA 0x58
|
|
#define BMI270_REG_INIT_CTRL 0x59
|
|
#define BMI270_REG_INIT_ADDR_0 0x5B
|
|
#define BMI270_REG_INIT_DATA 0x5E
|
|
#define BMI270_REG_INTERNAL_ERROR 0x5F
|
|
#define BMI270_REG_AUX_IF_TRIM 0x68
|
|
#define BMI270_REG_GYR_CRT_CONF 0x69
|
|
#define BMI270_REG_NVM_CONF 0x6A
|
|
#define BMI270_REG_IF_CONF 0x6B
|
|
#define BMI270_REG_DRV 0x6C
|
|
#define BMI270_REG_ACC_SELF_TEST 0x6D
|
|
#define BMI270_REG_GYR_SELF_TEST 0x6E
|
|
#define BMI270_REG_NV_CONF 0x70
|
|
#define BMI270_REG_OFFSET_0 0x71
|
|
#define BMI270_REG_PWR_CONF 0x7C
|
|
#define BMI270_REG_PWR_CTRL 0x7D
|
|
#define BMI270_REG_CMD 0x7E
|
|
|
|
#define BMI270_CHIP_ID 0x24
|
|
|
|
#define BMI270_CMD_G_TRIGGER 0x02
|
|
#define BMI270_CMD_USR_GAIN 0x03
|
|
#define BMI270_CMD_NVM_PROG 0xA0
|
|
#define BMI270_CMD_FIFO_FLUSH OxB0
|
|
#define BMI270_CMD_SOFT_RESET 0xB6
|
|
|
|
#define BMI270_POWER_ON_TIME 500
|
|
#define BMI270_SOFT_RESET_TIME 2000
|
|
#define BMI270_ACC_SUS_TO_NOR_START_UP_TIME 2000
|
|
#define BMI270_GYR_SUS_TO_NOR_START_UP_TIME 45000
|
|
#define BMI270_GYR_FAST_START_UP_TIME 2000
|
|
#define BMI270_TRANSC_DELAY_SUSPEND 450
|
|
#define BMI270_TRANSC_DELAY_NORMAL 2
|
|
|
|
#define BMI270_PREPARE_CONFIG_LOAD 0x00
|
|
#define BMI270_COMPLETE_CONFIG_LOAD 0x01
|
|
|
|
#define BMI270_INST_MESSAGE_MSK 0x0F
|
|
#define BMI270_INST_MESSAGE_NOT_INIT 0x00
|
|
#define BMI270_INST_MESSAGE_INIT_OK 0x01
|
|
#define BMI270_INST_MESSAGE_INIT_ERR 0x02
|
|
#define BMI270_INST_MESSAGE_DRV_ERR 0x03
|
|
#define BMI270_INST_MESSAGE_SNS_STOP 0x04
|
|
#define BMI270_INST_MESSAGE_NVM_ERR 0x05
|
|
#define BMI270_INST_MESSAGE_STRTUP_ERR 0x06
|
|
#define BMI270_INST_MESSAGE_COMPAT_ERR 0x07
|
|
|
|
#define BMI270_INST_AXES_REMAP_ERROR 0x20
|
|
#define BMI270_INST_ODR_50HZ_ERROR 0x40
|
|
|
|
#define BMI270_PWR_CONF_ADV_PWR_SAVE_MSK 0x01
|
|
#define BMI270_PWR_CONF_ADV_PWR_SAVE_EN 0x01
|
|
#define BMI270_PWR_CONF_ADV_PWR_SAVE_DIS 0x00
|
|
|
|
#define BMI270_PWR_CONF_FIFO_SELF_WKUP_MSK 0x02
|
|
#define BMI270_PWR_CONF_FIFO_SELF_WKUP_POS 0x01
|
|
#define BMI270_PWR_CONF_FIFO_SELF_WKUP_EN 0x01
|
|
#define BMI270_PWR_CONF_FIFO_SELF_WKUP_DIS 0x00
|
|
|
|
#define BMI270_PWR_CONF_FUP_EN_MSK 0x04
|
|
#define BMI270_PWR_CONF_FUP_EN_POS 0x02
|
|
#define BMI270_PWR_CONF_FUP_EN 0x01
|
|
#define BMI270_PWR_CONF_FUP_DIS 0x00
|
|
|
|
#define BMI270_PWR_CTRL_MSK 0x0F
|
|
#define BMI270_PWR_CTRL_AUX_EN 0x01
|
|
#define BMI270_PWR_CTRL_GYR_EN 0x02
|
|
#define BMI270_PWR_CTRL_ACC_EN 0x04
|
|
#define BMI270_PWR_CTRL_TEMP_EN 0x08
|
|
|
|
#define BMI270_ACC_ODR_MSK 0x0F
|
|
#define BMI270_ACC_ODR_25D32_HZ 0x01
|
|
#define BMI270_ACC_ODR_25D16_HZ 0x02
|
|
#define BMI270_ACC_ODR_25D8_HZ 0x03
|
|
#define BMI270_ACC_ODR_25D4_HZ 0x04
|
|
#define BMI270_ACC_ODR_25D2_HZ 0x05
|
|
#define BMI270_ACC_ODR_25_HZ 0x06
|
|
#define BMI270_ACC_ODR_50_HZ 0x07
|
|
#define BMI270_ACC_ODR_100_HZ 0x08
|
|
#define BMI270_ACC_ODR_200_HZ 0x09
|
|
#define BMI270_ACC_ODR_400_HZ 0x0A
|
|
#define BMI270_ACC_ODR_800_HZ 0x0B
|
|
#define BMI270_ACC_ODR_1600_HZ 0x0C
|
|
|
|
#define BMI270_ACC_BWP_MSK 0x30
|
|
#define BMI270_ACC_BWP_POS 4
|
|
#define BMI270_ACC_BWP_OSR4_AVG1 0x00
|
|
#define BMI270_ACC_BWP_OSR2_AVG2 0x01
|
|
#define BMI270_ACC_BWP_NORM_AVG4 0x02
|
|
#define BMI270_ACC_BWP_CIC_AVG8 0x03
|
|
#define BMI270_ACC_BWP_RES_AVG16 0x04
|
|
#define BMI270_ACC_BWP_RES_AVG32 0x05
|
|
#define BMI270_ACC_BWP_RES_AVG64 0x06
|
|
#define BMI270_ACC_BWP_RES_AVG128 0x07
|
|
|
|
#define BMI270_ACC_FILT_MSK 0x80
|
|
#define BMI270_ACC_FILT_POS 7
|
|
#define BMI270_ACC_FILT_PWR_OPT 0x00
|
|
#define BMI270_ACC_FILT_PERF_OPT 0x01
|
|
|
|
#define BMI270_ACC_RANGE_MSK 0x03
|
|
#define BMI270_ACC_RANGE_2G 0x00
|
|
#define BMI270_ACC_RANGE_4G 0x01
|
|
#define BMI270_ACC_RANGE_8G 0x02
|
|
#define BMI270_ACC_RANGE_16G 0x03
|
|
|
|
#define BMI270_GYR_ODR_MSK 0x0F
|
|
#define BMI270_GYR_ODR_25_HZ 0x06
|
|
#define BMI270_GYR_ODR_50_HZ 0x07
|
|
#define BMI270_GYR_ODR_100_HZ 0x08
|
|
#define BMI270_GYR_ODR_200_HZ 0x09
|
|
#define BMI270_GYR_ODR_400_HZ 0x0A
|
|
#define BMI270_GYR_ODR_800_HZ 0x0B
|
|
#define BMI270_GYR_ODR_1600_HZ 0x0C
|
|
#define BMI270_GYR_ODR_3200_HZ 0x0D
|
|
|
|
#define BMI270_GYR_BWP_MSK 0x30
|
|
#define BMI270_GYR_BWP_POS 4
|
|
#define BMI270_GYR_BWP_OSR4 0x00
|
|
#define BMI270_GYR_BWP_OSR2 0x01
|
|
#define BMI270_GYR_BWP_NORM 0x02
|
|
|
|
#define BMI270_GYR_FILT_NOISE_MSK 0x40
|
|
#define BMI270_GYR_FILT_NOISE_POS 6
|
|
#define BMI270_GYR_FILT_NOISE_PWR 0x00
|
|
#define BMI270_GYR_FILT_NOISE_PERF 0x01
|
|
|
|
#define BMI270_GYR_FILT_MSK 0x80
|
|
#define BMI270_GYR_FILT_POS 7
|
|
#define BMI270_GYR_FILT_PWR_OPT 0x00
|
|
#define BMI270_GYR_FILT_PERF_OPT 0x01
|
|
|
|
#define BMI270_GYR_RANGE_MSK 0x07
|
|
#define BMI270_GYR_RANGE_2000DPS 0x00
|
|
#define BMI270_GYR_RANGE_1000DPS 0x01
|
|
#define BMI270_GYR_RANGE_500DPS 0x02
|
|
#define BMI270_GYR_RANGE_250DPS 0x03
|
|
#define BMI270_GYR_RANGE_125DPS 0x04
|
|
|
|
#define BMI270_GYR_OIS_RANGE_MSK 0x80
|
|
#define BMI270_GYR_OIS_RANGE_POS 3
|
|
#define BMI270_GYR_OIS_RANGE_250DPS 0x00
|
|
#define BMI270_GYR_OIS_RANGE_2000DPS 0x01
|
|
|
|
#define BMI270_SET_BITS(reg_data, bitname, data) \
|
|
((reg_data & ~(bitname##_MSK)) | ((data << bitname##_POS) \
|
|
& bitname##_MSK))
|
|
#define BMI270_SET_BITS_POS_0(reg_data, bitname, data) \
|
|
((reg_data & ~(bitname##_MSK)) | (data & bitname##_MSK))
|
|
|
|
struct bmi270_data {
|
|
int16_t ax, ay, az, gx, gy, gz;
|
|
uint8_t acc_range, acc_odr, gyr_odr;
|
|
uint16_t gyr_range;
|
|
};
|
|
|
|
struct bmi270_dev_config {
|
|
struct i2c_dt_spec i2c;
|
|
};
|
|
|
|
#endif /* ZEPHYR_DRIVERS_SENSOR_BMI270_BMI270_H_ */
|