357 lines
9.8 KiB
C
357 lines
9.8 KiB
C
/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_watchdog
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/**
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* @file
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* @brief Nuvoton NPCX watchdog modules driver
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*
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* This file contains the drivers of NPCX Watchdog module that generates the
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* clocks and interrupts (T0 Timer) used for its callback functions in the
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* system. It also provides watchdog reset signal generation in response to a
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* failure detection. Please refer the block diagram for more detail.
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*
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* +---------------------+ +-----------------+
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* LFCLK --->| T0 Prescale Counter |-+->| 16-Bit T0 Timer |--------> T0 Timer
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* (32kHz) | (TWCP 1:32) | | | (TWDT0) | Event
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* +---------------------+ | +-----------------+
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* +---------------------------------+
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* |
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* | +-------------------+ +-----------------+
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* +--->| Watchdog Prescale |--->| 8-Bit Watchdog |-----> Watchdog Event/Reset
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* | (WDCP 1:32) | | Counter (WDCNT) | after n clocks
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* +-------------------+ +-----------------+
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*
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*/
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#include <assert.h>
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#include <drivers/gpio.h>
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#include <drivers/clock_control.h>
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#include <drivers/watchdog.h>
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#include <soc.h>
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#include "soc_miwu.h"
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#include <logging/log.h>
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LOG_MODULE_REGISTER(wdt_npcx, CONFIG_WDT_LOG_LEVEL);
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/* Watchdog operating frequency is fixed to LFCLK (32.768) kHz */
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#define NPCX_WDT_CLK LFCLK
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/*
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* Maximum watchdog window time. Since the watchdog counter is 8-bits, maximum
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* time supported by npcx watchdog is 256 * (32 * 32) / 32768 = 8 sec.
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*/
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#define NPCX_WDT_MAX_WND_TIME 8000UL
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/*
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* Minimum watchdog window time. Ensure we have waited at least 3 watchdog
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* clocks since touching WD timer. 3 / (32768 / 1024) HZ = 93.75ms
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*/
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#define NPCX_WDT_MIN_WND_TIME 100UL
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/* Timeout for reloading and restarting Timer 0. (Unit:ms) */
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#define NPCX_T0CSR_RST_TIMEOUT 2
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/* Timeout for stopping watchdog. (Unit:ms) */
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#define NPCX_WATCHDOG_STOP_TIMEOUT 1
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/* Device config */
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struct wdt_npcx_config {
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/* wdt controller base address */
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uintptr_t base;
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/* t0 timer wake-up input source configuration */
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const struct npcx_wui t0out;
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};
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/* Driver data */
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struct wdt_npcx_data {
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/* Timestamp of touching watchdog last time */
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int64_t last_watchdog_touch;
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/* Timeout callback used to handle watchdog event */
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wdt_callback_t cb;
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/* Watchdog feed timeout in milliseconds */
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uint32_t timeout;
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/* Indicate whether a watchdog timeout is installed */
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bool timeout_installed;
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};
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struct miwu_dev_callback miwu_cb;
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/* Driver convenience defines */
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#define DRV_CONFIG(dev) ((const struct wdt_npcx_config *)(dev)->config)
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#define DRV_DATA(dev) ((struct wdt_npcx_data *)(dev)->data)
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#define HAL_INSTANCE(dev) (struct twd_reg *)(DRV_CONFIG(dev)->base)
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/* WDT local inline functions */
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static inline int wdt_t0out_reload(const struct device *dev)
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{
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struct twd_reg *const inst = HAL_INSTANCE(dev);
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uint64_t st;
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/* Reload and restart T0 timer */
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inst->T0CSR = (inst->T0CSR & ~BIT(NPCX_T0CSR_WDRST_STS)) |
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BIT(NPCX_T0CSR_RST);
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/* Wait for timer is loaded and restart */
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st = k_uptime_get();
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while (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_RST)) {
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if (k_uptime_get() - st > NPCX_T0CSR_RST_TIMEOUT) {
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/* RST bit is still set? */
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if (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_RST)) {
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LOG_ERR("Timeout: reload T0 timer!");
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return -ETIMEDOUT;
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}
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}
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}
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return 0;
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}
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static inline int wdt_wait_stopped(const struct device *dev)
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{
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struct twd_reg *const inst = HAL_INSTANCE(dev);
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uint64_t st;
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st = k_uptime_get();
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/* If watchdog is still running? */
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while (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_WD_RUN)) {
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if (k_uptime_get() - st > NPCX_WATCHDOG_STOP_TIMEOUT) {
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/* WD_RUN bit is still set? */
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if (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_WD_RUN)) {
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LOG_ERR("Timeout: stop watchdog timer!");
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return -ETIMEDOUT;
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}
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}
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}
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return 0;
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}
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/* WDT local functions */
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static void wdt_t0out_isr(const struct device *dev, struct npcx_wui *wui)
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{
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struct wdt_npcx_data *const data = DRV_DATA(dev);
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ARG_UNUSED(wui);
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LOG_DBG("WDT reset will issue after %d delay cycle! WUI(%d %d %d)",
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CONFIG_WDT_NPCX_DELAY_CYCLES, wui->table, wui->group, wui->bit);
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/* Handle watchdog event here. */
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if (data->cb) {
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data->cb(dev, 0);
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}
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}
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static void wdt_config_t0out_interrupt(const struct device *dev)
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{
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const struct wdt_npcx_config *const config = DRV_CONFIG(dev);
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/* Initialize a miwu device input and its callback function */
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npcx_miwu_init_dev_callback(&miwu_cb, &config->t0out, wdt_t0out_isr,
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dev);
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npcx_miwu_manage_dev_callback(&miwu_cb, true);
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/*
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* Configure the T0 wake-up event triggered from a rising edge
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* on T0OUT signal.
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*/
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npcx_miwu_interrupt_configure(&config->t0out,
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NPCX_MIWU_MODE_EDGE, NPCX_MIWU_TRIG_HIGH);
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}
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/* WDT api functions */
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static int wdt_npcx_install_timeout(const struct device *dev,
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const struct wdt_timeout_cfg *cfg)
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{
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struct wdt_npcx_data *const data = DRV_DATA(dev);
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struct twd_reg *const inst = HAL_INSTANCE(dev);
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/* If watchdog is already running */
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if (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_WD_RUN)) {
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return -EBUSY;
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}
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/* No window watchdog support */
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if (cfg->window.min != 0) {
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data->timeout_installed = false;
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return -EINVAL;
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}
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/*
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* Since the watchdog counter in npcx series is 8-bits, maximum time
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* supported by it is 256 * (32 * 32) / 32768 = 8 sec. This makes the
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* allowed range of 1-8000 in milliseconds. Check if the provided value
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* is within this range.
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*/
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if (cfg->window.max > NPCX_WDT_MAX_WND_TIME || cfg->window.max == 0) {
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data->timeout_installed = false;
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return -EINVAL;
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}
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/* Save watchdog timeout */
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data->timeout = cfg->window.max;
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/* Install user timeout isr */
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data->cb = cfg->callback;
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data->timeout_installed = true;
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return 0;
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}
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static int wdt_npcx_setup(const struct device *dev, uint8_t options)
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{
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struct twd_reg *const inst = HAL_INSTANCE(dev);
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const struct wdt_npcx_config *const config = DRV_CONFIG(dev);
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struct wdt_npcx_data *const data = DRV_DATA(dev);
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int rv;
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/* Disable irq of t0-out expired event first */
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npcx_miwu_irq_disable(&config->t0out);
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if (!data->timeout_installed) {
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LOG_ERR("No valid WDT timeout installed");
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return -EINVAL;
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}
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if (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_WD_RUN)) {
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LOG_ERR("WDT timer is busy");
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return -EBUSY;
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}
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if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0) {
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LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP is not supported");
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return -ENOTSUP;
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}
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if ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) != 0) {
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LOG_ERR("WDT_OPT_PAUSE_HALTED_BY_DBG is not supported");
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return -ENOTSUP;
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}
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/*
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* One clock period of T0 timer is 32/32.768 KHz = 0.976 ms.
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* Then the counter value is timeout/0.976 - 1.
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*/
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inst->TWDT0 = MAX(ceiling_fraction(data->timeout * NPCX_WDT_CLK,
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32 * 1000) - 1, 1);
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/* Configure 8-bit watchdog counter */
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inst->WDCNT = MIN(ceiling_fraction(data->timeout, 32) +
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CONFIG_WDT_NPCX_DELAY_CYCLES, 0xff);
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LOG_DBG("WDT setup: TWDT0, WDCNT are %d, %d", inst->TWDT0, inst->WDCNT);
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/* Reload and restart T0 timer */
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rv = wdt_t0out_reload(dev);
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/* Configure t0 timer interrupt and its isr. */
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wdt_config_t0out_interrupt(dev);
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/* Enable irq of t0-out expired event */
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npcx_miwu_irq_enable(&config->t0out);
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return rv;
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}
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static int wdt_npcx_disable(const struct device *dev)
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{
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const struct wdt_npcx_config *const config = DRV_CONFIG(dev);
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struct wdt_npcx_data *const data = DRV_DATA(dev);
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struct twd_reg *const inst = HAL_INSTANCE(dev);
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/*
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* Ensure we have waited at least 3 watchdog ticks before
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* stopping watchdog
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*/
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while (k_uptime_get() - data->last_watchdog_touch <
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NPCX_WDT_MIN_WND_TIME)
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continue;
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/*
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* Stop and unlock watchdog by writing 87h, 61h and 63h
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* sequence bytes to WDSDM register
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*/
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inst->WDSDM = 0x87;
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inst->WDSDM = 0x61;
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inst->WDSDM = 0x63;
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/* Disable irq of t0-out expired event and mark it uninstalled */
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npcx_miwu_irq_disable(&config->t0out);
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data->timeout_installed = false;
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/* Wait for watchdof is stopped. */
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return wdt_wait_stopped(dev);
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}
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static int wdt_npcx_feed(const struct device *dev, int channel_id)
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{
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ARG_UNUSED(channel_id);
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struct wdt_npcx_data *const data = DRV_DATA(dev);
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struct twd_reg *const inst = HAL_INSTANCE(dev);
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/* Feed watchdog by writing 5Ch to WDSDM */
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inst->WDSDM = 0x5C;
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data->last_watchdog_touch = k_uptime_get();
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/* Reload and restart T0 timer */
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return wdt_t0out_reload(dev);
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}
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/* WDT driver registration */
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static const struct wdt_driver_api wdt_npcx_driver_api = {
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.setup = wdt_npcx_setup,
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.disable = wdt_npcx_disable,
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.install_timeout = wdt_npcx_install_timeout,
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.feed = wdt_npcx_feed,
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};
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static int wdt_npcx_init(const struct device *dev)
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{
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struct twd_reg *const inst = HAL_INSTANCE(dev);
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#ifdef CONFIG_WDT_DISABLE_AT_BOOT
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wdt_npcx_disable(dev);
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#endif
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/*
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* TWCFG (Timer Watchdog Configuration) setting
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* [7:6]- Reserved = 0
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* [5] - WDSDME = 1: Feed watchdog by writing 5Ch to WDSDM
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* [4] - WDCT0I = 1: Select T0IN as watchdog prescaler clock
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* [3] - LWDCNT = 0: Don't lock WDCNT register
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* [2] - LTWDT0 = 0: Don't lock TWDT0 register
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* [1] - LTWCP = 0: Don't lock TWCP register
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* [0] - LTWCFG = 0: Don't lock TWCFG register
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*/
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inst->TWCFG = BIT(NPCX_TWCFG_WDSDME) | BIT(NPCX_TWCFG_WDCT0I);
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/* Disable early touch functionality */
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inst->T0CSR = (inst->T0CSR & ~BIT(NPCX_T0CSR_WDRST_STS)) |
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BIT(NPCX_T0CSR_TESDIS);
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/*
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* Plan clock frequency of T0 timer and watchdog timer as below:
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* - T0 Timer freq is LFCLK/32 Hz
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* - Watchdog freq is T0CLK/32 Hz (ie. LFCLK/1024 Hz)
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*/
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inst->WDCP = 0x05; /* Prescaler is 32 in Watchdog Timer */
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inst->TWCP = 0x05; /* Prescaler is 32 in T0 Timer */
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return 0;
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}
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static const struct wdt_npcx_config wdt_npcx_cfg_0 = {
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.base = DT_INST_REG_ADDR(0),
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.t0out = NPCX_DT_WUI_ITEM_BY_NAME(0, t0_out)
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};
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static struct wdt_npcx_data wdt_npcx_data_0;
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DEVICE_DT_INST_DEFINE(0, wdt_npcx_init, NULL,
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&wdt_npcx_data_0, &wdt_npcx_cfg_0,
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PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&wdt_npcx_driver_api);
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