179 lines
6.2 KiB
C
179 lines
6.2 KiB
C
/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_s32_netc_vsi
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#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(nxp_s32_eth_vsi);
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/mbox.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/net/ethernet.h>
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#include <zephyr/net/net_if.h>
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#include <zephyr/net/net_pkt.h>
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#include <zephyr/net/phy.h>
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#include <ethernet/eth_stats.h>
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#include <soc.h>
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#include <Netc_Eth_Ip.h>
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#include <Netc_Eth_Ip_Irq.h>
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#include <Netc_EthSwt_Ip.h>
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#include "eth.h"
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#include "eth_nxp_s32_netc_priv.h"
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#define TX_RING_IDX 0
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#define RX_RING_IDX 0
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static void nxp_s32_eth_iface_init(struct net_if *iface)
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{
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const struct device *dev = net_if_get_device(iface);
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struct nxp_s32_eth_data *ctx = dev->data;
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const struct nxp_s32_eth_config *cfg = dev->config;
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const struct nxp_s32_eth_msix *msix;
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/*
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* For VLAN, this value is only used to get the correct L2 driver.
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* The iface pointer in context should contain the main interface
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* if the VLANs are enabled.
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*/
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if (ctx->iface == NULL) {
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ctx->iface = iface;
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}
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Netc_Eth_Ip_SetMacAddr(cfg->si_idx, (const uint8_t *)ctx->mac_addr);
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net_if_set_link_addr(iface, ctx->mac_addr, sizeof(ctx->mac_addr), NET_LINK_ETHERNET);
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LOG_INF("SI%d MAC: %02x:%02x:%02x:%02x:%02x:%02x", cfg->si_idx,
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ctx->mac_addr[0], ctx->mac_addr[1], ctx->mac_addr[2],
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ctx->mac_addr[3], ctx->mac_addr[4], ctx->mac_addr[5]);
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ethernet_init(iface);
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/* Assumes PSI is already started and link is up, iface will auto-start after init */
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net_eth_carrier_on(iface);
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for (int i = 0; i < NETC_MSIX_EVENTS_COUNT; i++) {
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msix = &cfg->msix[i];
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if (mbox_is_ready_dt(&msix->mbox_spec)) {
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if (mbox_set_enabled_dt(&msix->mbox_spec, true)) {
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LOG_ERR("Failed to enable MRU channel %u",
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msix->mbox_spec.channel_id);
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}
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}
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}
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}
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static const struct ethernet_api nxp_s32_eth_api = {
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.iface_api.init = nxp_s32_eth_iface_init,
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.get_capabilities = nxp_s32_eth_get_capabilities,
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.set_config = nxp_s32_eth_set_config,
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.send = nxp_s32_eth_tx
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};
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(nxp_s32_netc_vsi) == 1, "Only one VSI enabled supported");
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#define NETC_VSI_INSTANCE_DEFINE(n) \
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NETC_GENERATE_MAC_ADDRESS(n) \
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\
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void nxp_s32_eth_vsi##n##_rx_event(uint8_t chan, const uint32_t *buf, uint8_t buf_size) \
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{ \
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Netc_Eth_Ip_MSIX_Rx(NETC_SI_NXP_S32_HW_INSTANCE(n)); \
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} \
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\
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static void nxp_s32_eth##n##_rx_callback(const uint8_t unused, const uint8_t ring) \
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{ \
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const struct device *dev = DEVICE_DT_INST_GET(n); \
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const struct nxp_s32_eth_config *cfg = dev->config; \
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struct nxp_s32_eth_data *ctx = dev->data; \
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\
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if (ring == cfg->rx_ring_idx) { \
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k_sem_give(&ctx->rx_sem); \
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} \
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} \
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\
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static Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
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Netc_Eth_Ip_VsiToPsiMsgType nxp_s32_eth##n##_vsi2psi_msg \
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__aligned(FEATURE_NETC_ETH_VSI_MSG_ALIGNMENT); \
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static Netc_Eth_Ip_MACFilterHashTableEntryType \
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nxp_s32_eth##n##_mac_filter_hash_table[CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE]; \
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\
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NETC_RX_RING(n, TX_RING_IDX, CONFIG_ETH_NXP_S32_RX_RING_LEN, \
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CONFIG_ETH_NXP_S32_RX_RING_BUF_SIZE); \
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NETC_TX_RING(n, RX_RING_IDX, CONFIG_ETH_NXP_S32_TX_RING_LEN, \
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CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE); \
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\
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static const Netc_Eth_Ip_RxRingConfigType nxp_s32_eth##n##_rxring_cfg[1] = { \
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{ \
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.RingDesc = nxp_s32_eth##n##_rxring0_desc, \
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.Buffer = nxp_s32_eth##n##_rxring0_buf, \
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.ringSize = CONFIG_ETH_NXP_S32_RX_RING_LEN, \
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.maxRingSize = CONFIG_ETH_NXP_S32_RX_RING_LEN, \
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.bufferLen = CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE, \
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.maxBuffLen = CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE, \
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.TimerThreshold = CONFIG_ETH_NXP_S32_RX_IRQ_TIMER_THRESHOLD, \
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.PacketsThreshold = CONFIG_ETH_NXP_S32_RX_IRQ_PACKET_THRESHOLD, \
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.Callback = nxp_s32_eth##n##_rx_callback, \
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} \
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}; \
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static const Netc_Eth_Ip_TxRingConfigType nxp_s32_eth##n##_txring_cfg[1] = { \
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{ \
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.RingDesc = nxp_s32_eth##n##_txring0_desc, \
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.Buffer = nxp_s32_eth##n##_txring0_buf, \
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.ringSize = CONFIG_ETH_NXP_S32_TX_RING_LEN, \
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.maxRingSize = CONFIG_ETH_NXP_S32_TX_RING_LEN, \
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.bufferLen = CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE, \
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.maxBuffLen = CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE, \
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} \
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}; \
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\
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static const Netc_Eth_Ip_StationInterfaceConfigType nxp_s32_eth##n##_si_cfg = { \
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.NumberOfRxBDR = 1, \
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.NumberOfTxBDR = 1, \
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.txMruMailboxAddr = NULL, \
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.rxMruMailboxAddr = (uint32_t *)MRU_MBOX_ADDR(DT_DRV_INST(n), rx), \
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.RxInterrupts = (uint32_t)true, \
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.TxInterrupts = (uint32_t)false, \
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.MACFilterTableMaxNumOfEntries = CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE, \
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.VSItoPSIMsgCommand = &nxp_s32_eth##n##_vsi2psi_msg, \
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}; \
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\
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static struct nxp_s32_eth_data nxp_s32_eth##n##_data = { \
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.mac_addr = DT_INST_PROP_OR(n, local_mac_address, {0}), \
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}; \
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\
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static const struct nxp_s32_eth_config nxp_s32_eth##n##_cfg = { \
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.netc_cfg = { \
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.SiType = NETC_ETH_IP_VIRTUAL_SI, \
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.siConfig = &nxp_s32_eth##n##_si_cfg, \
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.stateStructure = &nxp_s32_eth##n##_state, \
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.paCtrlRxRingConfig = &nxp_s32_eth##n##_rxring_cfg, \
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.paCtrlTxRingConfig = &nxp_s32_eth##n##_txring_cfg, \
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}, \
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.si_idx = NETC_SI_NXP_S32_HW_INSTANCE(n), \
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.tx_ring_idx = TX_RING_IDX, \
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.rx_ring_idx = RX_RING_IDX, \
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.msix = { \
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NETC_MSIX(DT_DRV_INST(n), rx, nxp_s32_eth_vsi##n##_rx_event), \
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}, \
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.mac_filter_hash_table = &nxp_s32_eth##n##_mac_filter_hash_table[0], \
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.generate_mac = nxp_s32_eth##n##_generate_mac, \
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}; \
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\
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ETH_NET_DEVICE_DT_INST_DEFINE(n, \
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nxp_s32_eth_initialize_common, \
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NULL, \
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&nxp_s32_eth##n##_data, \
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&nxp_s32_eth##n##_cfg, \
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CONFIG_ETH_NXP_S32_VSI_INIT_PRIORITY, \
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&nxp_s32_eth_api, \
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NET_ETH_MTU);
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DT_INST_FOREACH_STATUS_OKAY(NETC_VSI_INSTANCE_DEFINE)
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