132 lines
3.4 KiB
C
132 lines
3.4 KiB
C
/*
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* Driver for Synopsys DesignWare MAC
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*
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* Copyright (c) 2021 BayLibre SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* STM32H7X specific glue.
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*/
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#define LOG_MODULE_NAME dwmac_plat
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#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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/* be compatible with the HAL-based driver here */
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#define DT_DRV_COMPAT st_stm32_ethernet
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#include <sys/types.h>
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#include <zephyr/kernel.h>
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#include <zephyr/net/ethernet.h>
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#include <ethernet/eth.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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#include "eth_dwmac_priv.h"
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PINCTRL_DT_INST_DEFINE(0);
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static const struct pinctrl_dev_config *eth0_pcfg =
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PINCTRL_DT_INST_DEV_CONFIG_GET(0);
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static const struct stm32_pclken pclken = {
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.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bus),
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.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits),
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};
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static const struct stm32_pclken pclken_tx = {
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.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bus),
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.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bits),
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};
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static const struct stm32_pclken pclken_rx = {
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.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bus),
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.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bits),
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};
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int dwmac_bus_init(struct dwmac_priv *p)
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{
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uint32_t reg_addr, reg_val;
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int ret;
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p->clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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if (!device_is_ready(p->clock)) {
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LOG_ERR("clock control device not ready");
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return -ENODEV;
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}
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ret = clock_control_on(p->clock, (clock_control_subsys_t)&pclken);
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ret |= clock_control_on(p->clock, (clock_control_subsys_t)&pclken_tx);
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ret |= clock_control_on(p->clock, (clock_control_subsys_t)&pclken_rx);
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if (ret) {
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LOG_ERR("Failed to enable ethernet clock");
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return -EIO;
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}
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ret = pinctrl_apply_state(eth0_pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("Could not configure ethernet pins");
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return ret;
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}
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/* set SYSCFGEN in RCC_APB4ENR */
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reg_addr = DT_REG_ADDR(DT_INST(0, st_stm32h7_rcc)) + 0xf4;
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reg_val = sys_read32(reg_addr);
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sys_write32(reg_val | BIT(1), reg_addr);
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/* set RMII mode in SYSCFG_PMCR */
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reg_addr = 0x58000404; /* no DT node? */
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reg_val = sys_read32(reg_addr);
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sys_write32(reg_val | 0x03800000, reg_addr);
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p->base_addr = DT_INST_REG_ADDR(0);
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return 0;
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}
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#if defined(CONFIG_NOCACHE_MEMORY)
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#define __desc_mem __nocache __aligned(4)
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#else
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#error "missing memory attribute for descriptors"
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#endif
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/* Descriptor rings in uncached memory */
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static struct dwmac_dma_desc dwmac_tx_descs[NB_TX_DESCS] __desc_mem;
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static struct dwmac_dma_desc dwmac_rx_descs[NB_RX_DESCS] __desc_mem;
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void dwmac_platform_init(struct dwmac_priv *p)
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{
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p->tx_descs = dwmac_tx_descs;
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p->rx_descs = dwmac_rx_descs;
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/* basic configuration for this platform */
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REG_WRITE(MAC_CONF,
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MAC_CONF_PS |
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MAC_CONF_FES |
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MAC_CONF_DM);
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REG_WRITE(DMA_SYSBUS_MODE,
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DMA_SYSBUS_MODE_AAL |
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DMA_SYSBUS_MODE_FB);
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/* set up IRQs (still masked for now) */
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), dwmac_isr,
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DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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/* create MAC address */
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gen_random_mac(p->mac_addr, 0x00, 0x80, 0xE1);
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}
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/* Our private device instance */
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static struct dwmac_priv dwmac_instance;
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ETH_NET_DEVICE_DT_INST_DEFINE(0,
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dwmac_probe,
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NULL,
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&dwmac_instance,
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NULL,
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CONFIG_ETH_INIT_PRIORITY,
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&dwmac_api,
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NET_ETH_MTU);
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