63 lines
1.7 KiB
C
63 lines
1.7 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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/**
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* Flush the entire instruction cache and pipeline.
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*
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* You will need to call this function if the application writes new program
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* text to memory, such as a boot copier or runtime synthesis of code. If the
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* new text was written with instructions that do not bypass cache memories,
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* this should immediately be followed by an invocation of
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* _nios2_dcache_flush_all() so that cached instruction data is committed to
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* RAM.
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*
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* See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more
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* information on cache considerations.
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*/
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#if ALT_CPU_ICACHE_SIZE > 0
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void _nios2_icache_flush_all(void)
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{
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u32_t i;
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for (i = 0; i < ALT_CPU_ICACHE_SIZE; i += ALT_CPU_ICACHE_LINE_SIZE) {
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_nios2_icache_flush(i);
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}
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/* Get rid of any stale instructions in the pipeline */
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_nios2_pipeline_flush();
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}
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#endif
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/**
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* Flush the entire data cache.
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*
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* This will be typically needed after writing new program text to memory
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* after flushing the instruction cache.
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*
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* The Nios II does not support hardware cache coherency for multi-master
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* or multi-processor systems and software coherency must be implemented
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* when communicating with shared memory. If support for this is introduced
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* in Zephyr additional APIs for flushing ranges of the data cache will need
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* to be implemented.
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*
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* See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more
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* information on cache considerations.
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*/
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#if ALT_CPU_DCACHE_SIZE > 0
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void _nios2_dcache_flush_all(void)
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{
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u32_t i;
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for (i = 0; i < ALT_CPU_DCACHE_SIZE; i += ALT_CPU_DCACHE_LINE_SIZE) {
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_nios2_dcache_flush(i);
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}
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}
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#endif
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