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zephyr/boards/riscv/qemu_riscv32
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Shawn Nematbakhsh c74526919d soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS. 
Rather than specify input clock for each peripheral individually, instead
specify the relevant clocks in DTS.

This will enable easier support for non-default coreclk on fe310 in a
follow-up CL.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
 		2022-04-05 12:00:03 +02:00
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doc
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Kconfig.board boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp 2022-02-25 19:13:50 -05:00
Kconfig.defconfig boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp 2022-02-25 19:13:50 -05:00
board.cmake boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp 2022-02-25 19:13:50 -05:00
qemu_riscv32.dts
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qemu_riscv32.yaml
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qemu_riscv32_defconfig
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qemu_riscv32_smp.dts boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp 2022-02-25 19:13:50 -05:00
qemu_riscv32_smp.yaml boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp 2022-02-25 19:13:50 -05:00
qemu_riscv32_smp_defconfig boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp 2022-02-25 19:13:50 -05:00
qemu_riscv32_xip-pinctrl.dtsi boards: qemu_riscv32: add pinctrl configuration for qemu_riscv32_xip 2022-03-24 10:46:34 +01:00
qemu_riscv32_xip.dts soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS. 2022-04-05 12:00:03 +02:00
qemu_riscv32_xip.yaml
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qemu_riscv32_xip_defconfig boards: FE310-based boards: transition to pinctrl driver 2022-03-24 10:46:34 +01:00