72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
/*
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* Copyright (c) 2020 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <soc_pinmap.h>
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#include <cmsis_core.h>
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void eos_s3_lock_enable(void)
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{
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MISC_CTRL->LOCK_KEY_CTRL = MISC_LOCK_KEY;
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}
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void eos_s3_lock_disable(void)
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{
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MISC_CTRL->LOCK_KEY_CTRL = 1;
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}
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static void eos_s3_cru_init(void)
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{
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/* Set desired frequency */
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AIP->OSC_CTRL_0 |= AIP_OSC_CTRL_EN;
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AIP->OSC_CTRL_0 &= ~AIP_OSC_CTRL_FRE_SEL;
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OSC_SET_FREQ_INC(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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while (!OSC_CLK_LOCKED()) {
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;
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}
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/* Enable all clocks for every domain */
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CRU->CLK_DIVIDER_CLK_GATING = (CLK_DIVIDER_A_CG | CLK_DIVIDER_B_CG
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| CLK_DIVIDER_C_CG | CLK_DIVIDER_D_CG | CLK_DIVIDER_F_CG
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| CLK_DIVIDER_G_CG | CLK_DIVIDER_H_CG | CLK_DIVIDER_I_CG
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| CLK_DIVIDER_J_CG);
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/* Turn off divisor for A0 domain */
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CRU->CLK_CTRL_A_0 = 0;
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/* Enable UART, WDT and TIMER peripherals */
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CRU->C11_CLK_GATE = C11_CLK_GATE_PATH_0_ON;
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/* Set divider for domain C11 to ~ 5.12MHz */
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CRU->CLK_CTRL_D_0 = (CLK_CTRL_CLK_DIVIDER_ENABLE |
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CLK_CTRL_CLK_DIVIDER_RATIO_12);
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}
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static int eos_s3_init(void)
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{
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/* Clocks setup */
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eos_s3_lock_enable();
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eos_s3_cru_init();
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eos_s3_lock_disable();
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SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
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/* Clear all interrupts */
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INTR_CTRL->OTHER_INTR = 0xFFFFFF;
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/* Enable UART interrupt */
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INTR_CTRL->OTHER_INTR_EN_M4 = UART_INTR_EN_M4;
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return 0;
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}
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SYS_INIT(eos_s3_init, PRE_KERNEL_1, 0);
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