121 lines
3.7 KiB
C
121 lines
3.7 KiB
C
/*
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* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Pin control driver for Infineon CAT1 MCU family.
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <cyhal_gpio.h>
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#include <cy_gpio.h>
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#define GPIO_PORT_OR_NULL(node_id) \
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COND_CODE_1(DT_NODE_EXISTS(node_id), ((GPIO_PRT_Type *)DT_REG_ADDR(node_id)), (NULL))
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/* @brief Array containing pointers to each GPIO port.
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*
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* Entries will be NULL if the GPIO port is not enabled.
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*/
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static GPIO_PRT_Type *const gpio_ports[] = {
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt0)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt1)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt2)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt3)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt4)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt5)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt6)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt7)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt8)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt9)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt10)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt11)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt12)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt13)),
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GPIO_PORT_OR_NULL(DT_NODELABEL(gpio_prt14))
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};
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/* @brief This function returns gpio drive mode, according to.
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* bias and drive mode params defined in pinctrl node.
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*
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* @param flags - bias and drive mode flags from pinctrl node.
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*/
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static uint32_t soc_gpio_get_drv_mode(uint32_t flags)
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{
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uint32_t drv_mode = CY_GPIO_DM_ANALOG;
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uint32_t _flags;
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_flags = ((flags & SOC_GPIO_FLAGS_MASK) >> SOC_GPIO_FLAGS_POS);
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if (_flags & SOC_GPIO_OPENDRAIN) {
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/* drive_open_drain */
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drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESLOW
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: CY_GPIO_DM_OD_DRIVESLOW_IN_OFF;
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} else if (_flags & SOC_GPIO_OPENSOURCE) {
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/* drive_open_source */
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drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_OD_DRIVESHIGH
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: CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF;
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} else if (_flags & SOC_GPIO_PUSHPULL) {
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/* drive_push_pull */
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drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_STRONG
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: CY_GPIO_DM_STRONG_IN_OFF;
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} else if ((_flags & SOC_GPIO_PULLUP) && (_flags & SOC_GPIO_PULLDOWN)) {
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/* bias_pull_up and bias_pull_down */
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drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP_DOWN
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: CY_GPIO_DM_PULLUP_DOWN_IN_OFF;
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} else if (_flags & SOC_GPIO_PULLUP) {
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/* bias_pull_up */
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drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLUP
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: CY_GPIO_DM_PULLUP_IN_OFF;
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} else if (_flags & SOC_GPIO_PULLDOWN) {
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/* bias_pull_down */
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drv_mode = (_flags & SOC_GPIO_INPUTENABLE) ? CY_GPIO_DM_PULLDOWN
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: CY_GPIO_DM_PULLDOWN_IN_OFF;
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} else if ((_flags & SOC_GPIO_HIGHZ) | (_flags & SOC_GPIO_INPUTENABLE)) {
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/* bias_pull_down */
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drv_mode = CY_GPIO_DM_HIGHZ;
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} else {
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/* nothing do here */
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}
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return drv_mode;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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uint32_t drv_mode = soc_gpio_get_drv_mode(pins[i].pincfg);
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uint32_t hsiom = CAT1_PINMUX_GET_HSIOM_FUNC(pins[i].pinmux);
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uint32_t port_num = CAT1_PINMUX_GET_PORT_NUM(pins[i].pinmux);
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uint32_t pin_num = CAT1_PINMUX_GET_PIN_NUM(pins[i].pinmux);
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/* Initialize pin */
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Cy_GPIO_Pin_FastInit(gpio_ports[port_num], pin_num, drv_mode, 1, hsiom);
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/* Force output to enable pulls */
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switch (drv_mode) {
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case CY_GPIO_DM_PULLUP:
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Cy_GPIO_Write(gpio_ports[port_num], pin_num, 1);
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break;
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case CY_GPIO_DM_PULLDOWN:
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Cy_GPIO_Write(gpio_ports[port_num], pin_num, 0);
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break;
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default:
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/* do nothing */
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break;
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}
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}
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return 0;
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}
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