170 lines
4.2 KiB
C
170 lines
4.2 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#if defined(RCC_CFGR_USBPRE)
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#define STM32_USB_PRE_ENABLED RCC_CFGR_USBPRE
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#elif defined(RCC_CFGR_OTGFSPRE)
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#define STM32_USB_PRE_ENABLED RCC_CFGR_OTGFSPRE
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#endif
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#define z_adc_prescaler(v) LL_RCC_ADC_CLKSRC_PCLK2_DIV_ ## v
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#define adc_prescaler(v) z_adc_prescaler(v)
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#if defined(STM32_PLL_ENABLED)
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/*
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* Select PLL source for STM32F1 Connectivity line devices (STM32F105xx and
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* STM32F107xx).
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* Both flags are defined in STM32Cube LL API. Keep only the selected one.
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*/
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/**
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* @brief Set up pll configuration
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*/
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__unused
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void config_pll_sysclock(void)
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{
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uint32_t pll_source, pll_mul, pll_div;
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/*
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* PLLMUL on SOC_STM32F10X_DENSITY_DEVICE
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* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
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* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
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*
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* PLLMUL on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 9 -> LL_RCC_PLL_MUL_9 -> 0x001C0000
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* 13 -> LL_RCC_PLL_MUL_6_5 -> 0x00340000
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*/
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pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMULL_Pos);
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if (!IS_ENABLED(STM32_PLL_SRC_HSI)) {
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/* In case PLL source is not HSI, set prediv case by case */
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#ifdef CONFIG_SOC_STM32F10X_DENSITY_DEVICE
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/* PLL prediv */
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if (IS_ENABLED(STM32_PLL_XTPRE)) {
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/*
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* SOC_STM32F10X_DENSITY_DEVICE:
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* PLLXPTRE (depends on PLL source HSE)
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* HSE/2 used as PLL source
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*/
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pll_div = LL_RCC_PREDIV_DIV_2;
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} else {
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/*
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* SOC_STM32F10X_DENSITY_DEVICE:
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* PLLXPTRE (depends on PLL source HSE)
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* HSE used as direct PLL source
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*/
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pll_div = LL_RCC_PREDIV_DIV_1;
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}
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#else
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/*
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* SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
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* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
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* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
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* ...
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* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
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*/
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pll_div = STM32_PLL_PREDIV - 1;
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#endif /* CONFIG_SOC_STM32F10X_DENSITY_DEVICE */
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}
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/* Configure PLL source */
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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pll_source = LL_RCC_PLLSOURCE_HSI_DIV_2;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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pll_source = LL_RCC_PLLSOURCE_HSE | pll_div;
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#if defined(RCC_CFGR2_PREDIV1SRC)
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} else if (IS_ENABLED(STM32_PLL_SRC_PLL2)) {
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pll_source = LL_RCC_PLLSOURCE_PLL2 | pll_div;
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#endif
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} else {
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__ASSERT(0, "Invalid source");
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}
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LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul);
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#ifdef STM32_USB_PRE_ENABLED
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/* Prescaler is enabled: PLL clock is not divided */
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LL_RCC_SetUSBClockSource(IS_ENABLED(STM32_PLL_USBPRE) ?
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STM32_USB_PRE_ENABLED : 0);
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#endif
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}
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#endif /* defined(STM32_PLL_ENABLED) */
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#if defined(STM32_PLL2_ENABLED)
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/**
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* @brief Set up pll2 configuration
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*/
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__unused
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void config_pll2(void)
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{
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uint32_t pll_mul, pll_div;
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/*
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* PLL2MUL on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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* 8 -> LL_RCC_PLL2_MUL_8 -> 0x00000600
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* 9 -> LL_RCC_PLL2_MUL_9 -> 0x00000700
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* ...
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* 14 -> LL_RCC_PLL2_MUL_14 -> 0x00000C00
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* 16 -> LL_RCC_PLL2_MUL_16 -> 0x00000E00
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* 20 -> LL_RCC_PLL2_MUL_20 -> 0x00000F00
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*/
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if (STM32_PLL2_MULTIPLIER == 20) {
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pll_mul = RCC_CFGR2_PLL2MUL20;
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} else {
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pll_mul = ((STM32_PLL2_MULTIPLIER - 2) << RCC_CFGR2_PLL2MUL_Pos);
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}
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/*
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* SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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* 1 -> LL_RCC_HSE_PREDIV2_DIV_1 -> 0x00000000
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* 2 -> LL_RCC_HSE_PREDIV2_DIV_2 -> 0x00000010
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* ...
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* 16 -> LL_RCC_HSE_PREDIV2_DIV_16 -> 0x000000F0
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*/
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pll_div = ((STM32_PLL2_PREDIV - 1) << RCC_CFGR2_PREDIV2_Pos);
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/* Check PLL2 source */
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if (!IS_ENABLED(STM32_PLL2_SRC_HSE)) {
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__ASSERT(0, "Invalid source");
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}
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LL_RCC_PLL_ConfigDomain_PLL2(pll_div, pll_mul);
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}
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#endif /* defined(STM32_PLL2_ENABLED) */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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if (IS_ENABLED(STM32_LSE_ENABLED)) {
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/* Set the PWREN and BKPEN bits in the RCC_APB1ENR register */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_BKP);
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}
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}
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