171 lines
4.7 KiB
C
171 lines
4.7 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Exception/interrupt context helpers for Cortex-M CPUs
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*
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* Exception/interrupt context helpers.
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*/
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#ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_EXC_H_
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#define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_EXC_H_
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#include <arch/cpu.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef _ASMLANGUAGE
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/* nothing */
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#else
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#include <arch/arm/cortex_m/cmsis.h>
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#include <arch/arm/cortex_m/exc.h>
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#include <irq_offload.h>
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#ifdef CONFIG_IRQ_OFFLOAD
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extern volatile irq_offload_routine_t offload_routine;
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#endif
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/* Writes to the AIRCR must be accompanied by a write of the value 0x05FA
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* to the Vector Key field, otherwise the writes are ignored.
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*/
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#define AIRCR_VECT_KEY_PERMIT_WRITE 0x05FAUL
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/**
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*
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* @brief Find out if running in an ISR context
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*
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* The current executing vector is found in the IPSR register. We consider the
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* IRQs (exception 16 and up), and the PendSV and SYSTICK exceptions to be
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* interrupts. Taking a fault within an exception is also considered in
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* interrupt context.
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*
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* @return 1 if in ISR, 0 if not.
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*/
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static ALWAYS_INLINE bool z_IsInIsr(void)
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{
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u32_t vector = __get_IPSR();
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/* IRQs + PendSV (14) + SYSTICK (15) are interrupts. */
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return (vector > 13)
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#ifdef CONFIG_IRQ_OFFLOAD
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/* Only non-NULL if currently running an offloaded function */
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|| offload_routine != NULL
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#endif
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* On ARMv6-M there is no nested execution bit, so we check
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* exception 3, hard fault, to a detect a nested exception.
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*/
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|| (vector == 3U)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* If not in thread mode, and if RETTOBASE bit in ICSR is 0,
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* then there are preempted active exceptions to execute.
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*/
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#ifndef CONFIG_BOARD_QEMU_CORTEX_M3
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/* The polarity of RETTOBASE is incorrectly flipped in
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* all but the very latest master tip of QEMU's NVIC driver,
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* see commit "armv7m: Rewrite NVIC to not use any GIC code".
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* Until QEMU 2.9 is released, and the SDK is updated to
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* include it, skip this check in QEMU.
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*/
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|| (vector && !(SCB->ICSR & SCB_ICSR_RETTOBASE_Msk))
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#endif /* CONFIG_BOARD_QEMU_CORTEX_M3 */
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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;
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}
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/**
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* @brief Setup system exceptions
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*
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* Set exception priorities to conform with the BASEPRI locking mechanism.
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* Set PendSV priority to lowest possible.
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*
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* Enable fault exceptions.
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void z_ExcSetup(void)
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{
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NVIC_SetPriority(PendSV_IRQn, 0xff);
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#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
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NVIC_SetPriority(SVCall_IRQn, _EXC_SVC_PRIO);
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#endif
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#ifdef CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
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NVIC_SetPriority(MemoryManagement_IRQn, _EXC_FAULT_PRIO);
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NVIC_SetPriority(BusFault_IRQn, _EXC_FAULT_PRIO);
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NVIC_SetPriority(UsageFault_IRQn, _EXC_FAULT_PRIO);
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#if defined(CONFIG_ARM_SECURE_FIRMWARE)
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NVIC_SetPriority(SecureFault_IRQn, _EXC_FAULT_PRIO);
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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/* Enable Usage, Mem, & Bus Faults */
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SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
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SCB_SHCSR_BUSFAULTENA_Msk;
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#if defined(CONFIG_ARM_SECURE_FIRMWARE)
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/* Enable Secure Fault */
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SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk;
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/* Clear BFAR before setting BusFaults to target Non-Secure state. */
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SCB->BFAR = 0;
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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#endif /* CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS */
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#if defined(CONFIG_ARM_SECURE_FIRMWARE)
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/* Set NMI, Hard, and Bus Faults as Non-Secure.
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* NMI and Bus Faults targeting the Secure state will
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* escalate to a SecureFault or SecureHardFault.
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*/
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SCB->AIRCR =
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(SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk)))
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| SCB_AIRCR_BFHFNMINS_Msk
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| ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos) &
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SCB_AIRCR_VECTKEY_Msk);
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/* Note: Fault conditions that would generate a SecureFault
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* in a PE with the Main Extension instead generate a
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* SecureHardFault in a PE without the Main Extension.
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*/
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#endif /* CONFIG_ARM_SECURE_FIRMWARE */
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}
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/**
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* @brief Clear Fault exceptions
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*
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* Clear out exceptions for Mem, Bus, Usage and Hard Faults
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void z_clearfaults(void)
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{
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* Reset all faults */
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SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
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SCB_CFSR_MEMFAULTSR_Msk |
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SCB_CFSR_BUSFAULTSR_Msk;
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/* Clear all Hard Faults - HFSR is write-one-to-clear */
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SCB->HFSR = 0xffffffff;
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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}
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_EXC_H_ */
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