zephyr/soc/riscv
Yong Cong Sin 5b9f82668b riscv: telink_b91: fix compilation
Fix compilation failure due to multilevel interrupt.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-18 13:03:45 -04:00
..
espressif_esp32 soc: espressif: provide VMA to rodata and text by default 2023-09-18 10:38:03 +01:00
litex-vexriscv soc: riscv: Add ability to use custom sys_io functions 2023-07-26 09:43:59 +02:00
openisa_rv32m1 include: arch: arm: Remove aarch32 directory 2023-09-13 10:08:05 +01:00
riscv-ite ITE: drivers/i2c/target: Introduce I2C target transfer using PIO mode 2023-09-07 09:43:06 +02:00
riscv-privileged riscv: telink_b91: fix compilation 2023-09-18 13:03:45 -04:00
CMakeLists.txt