501 lines
12 KiB
Plaintext
501 lines
12 KiB
Plaintext
# Kconfig - STM32 MCU clock control driver config
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#
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# Copyright (c) 2017 Linaro
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# Copyright (c) 2017 RnDity Sp. z o.o.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_FAMILY_STM32
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menuconfig CLOCK_CONTROL_STM32_CUBE
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bool "STM32 Reset & Clock Control"
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depends on CLOCK_CONTROL
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select USE_STM32_LL_UTILS
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help
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Enable driver for Reset & Clock Control subsystem found
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in STM32 family of MCUs
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if CLOCK_CONTROL_STM32_CUBE
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config CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY
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int "Clock Control Device Priority"
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default 1
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help
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This option controls the priority of clock control
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device initialization. Higher priority ensures that the device
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is initialized earlier in the startup cycle. If unsure, leave
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at default value 1
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choice CLOCK_STM32_SYSCLK_SRC
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prompt "STM32 System Clock Source"
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config CLOCK_STM32_SYSCLK_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of SYSCLK
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config CLOCK_STM32_SYSCLK_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of SYSCLK
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config CLOCK_STM32_SYSCLK_SRC_MSI
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bool "MSI"
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depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X
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help
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Use MSI as source of SYSCLK
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config CLOCK_STM32_SYSCLK_SRC_PLL
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bool "PLL"
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help
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Use PLL as source of SYSCLK
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endchoice #CLOCK_STM32_SYSCLK_SRC
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config CLOCK_STM32_HSE_BYPASS
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bool "HSE bypass"
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depends on CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE
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help
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Enable this option to bypass external high-speed clock (HSE).
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config CLOCK_STM32_HSE_CLOCK
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int "HSE clock value"
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depends on CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE
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default 8000000
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help
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Value of external high-speed clock (HSE).
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config CLOCK_STM32_MSI_RANGE
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int "MSI frequency range"
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depends on CLOCK_STM32_SYSCLK_SRC_MSI
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default 8
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help
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Frequency range of MSI when MSI range is provided in RCC_CR register
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Range 0: 100kHz
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Range 1: 200kHz
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Range 2 around 400 kHz
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Range 3 around 800 kHz
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Range 4: 1 MHz
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Range 5: 2 MHz
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Range 6: 4 MHz (reset value)
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Range 7: 8 MHz
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Range 8: 16 MHz
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Range 9: 24 MHz
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Range 10: 32 MHz
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Range 11: 48 MHz
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choice
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prompt "STM32 PLL Clock Source"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default CLOCK_STM32_PLL_SRC_HSI
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config CLOCK_STM32_PLL_SRC_MSI
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bool "MSI"
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depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X
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help
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Use MSI as source of PLL
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config CLOCK_STM32_PLL_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of PLL
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config CLOCK_STM32_PLL_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of PLL
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config CLOCK_STM32_PLL_SRC_PLL2
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bool "PLL2"
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depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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help
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Use PLL2 as source of main PLL. This is equivalent of defining
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PLL2 as source PREDIV1SCR. If not selected, default source is HSE.
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endchoice
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if SOC_SERIES_STM32F0X
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config CLOCK_STM32_PLL_PREDIV
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int "PREDIV Prescaler"
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default 1
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range 1 16
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help
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PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16.
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config CLOCK_STM32_PLL_PREDIV1
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int "PREDIV1 Prescaler"
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depends on CLOCK_STM32_PLL_SRC_HSE
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default 1
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range 1 16
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help
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PREDIV is PLLSCR clock signal prescaler, present on STM32F0 SoC having
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an HSE Oscillator available like the stm32f04xx, stm32f07xx,
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stm32f09xx and stm32f030xc parts. If configured on a non supported
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part, the HSI oscillator will be used a default PLL source and this
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config will be ignored.
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Allowed values: 1 - 16.
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config CLOCK_STM32_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 6
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range 2 16
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help
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PLL multiplier, allowed values: 2-16. PLL output must not exceed 48MHz.
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endif # SOC_SERIES_STM32F0X
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if SOC_SERIES_STM32F1X
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config CLOCK_STM32_PLL_XTPRE
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bool "HSE to PLL /2 prescaler"
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depends on SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_PLL_SRC_HSE
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help
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Enable this option to enable /2 prescaler on HSE to PLL clock signal
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config CLOCK_STM32_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 9
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range 2 16 if SOC_STM32F10X_DENSITY_DEVICE
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range 4 9 if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
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help
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PLL multiplier, PLL output must not exceed 72MHz. Allowed values:
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Density devices: 2-16
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Connectivity devices: 4 - 9 and 13 ( used for multiplication factor 6.5).
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config CLOCK_STM32_PLL_PREDIV1
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int "PREDIV1 Prescaler"
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depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL
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default 1
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range 1 16
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help
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PREDIV1 is PLL clock signal prescaler, allowed values: 1 - 16.
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config CLOCK_STM32_PLL2_MULTIPLIER
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int "PLL2 multiplier"
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depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_PLL_SRC_PLL2
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default 8
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range 8 20
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help
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PLL2 multiplier, allowed values: 8 - 20. 15-17-18-19 reserved
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config CLOCK_STM32_PLL2_PREDIV2
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int "PREDIV2 Prescaler"
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depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_PLL_SRC_PLL2
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default 1
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range 1 16
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help
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PREDIV2 is PLL2 prescaler, allowed values: 1 - 16.
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endif # SOC_SERIES_STM32F1X
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if SOC_SERIES_STM32F2X
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config CLOCK_STM32_PLL_M_DIVISOR
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int "Division factor for PLL VCO input clock"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 20
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range 2 63
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help
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PLLM division factor needs to be set correctly to ensure that the VCO
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input frequency ranges from 1 to 2 MHz. It is recommended to select a
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frequency of 2 MHz to limit PLL jitter.
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Allowed values: 2-63
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "Multiplier factor for PLL VCO output clock"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 192
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range 192 432
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help
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PLLN multiplier factor needs to be set correctly to ensure that the
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VCO output frequency is between 192 and 432 MHz.
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL division factor for main system clock"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 2 8
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help
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PLLP division factor needs to be set correctly to not exceed 120MHz.
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Allowed values: 2, 4, 6, 8
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "PLL division factor for USB OTG FS, SDIO and RNG clocks"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 5
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range 2 15
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help
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The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
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need a frequency lower than or equal to 48 MHz to work correctly.
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Allowed values: 2-15
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endif # SOC_SERIES_STM32F2X
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if SOC_SERIES_STM32F3X
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config CLOCK_STM32_PLL_PREDIV
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int "PREDIV Prescaler"
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default 1
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range 1 16
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help
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PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16.
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config CLOCK_STM32_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 9
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range 2 16
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help
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PLL multiplier, allowed values: 2-16. PLL output must not exceed 72MHz.
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endif # SOC_SERIES_STM32F3X
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if SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
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config CLOCK_STM32_PLL_M_DIVISOR
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int "Division factor for PLL VCO input clock"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 8
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range 2 63
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help
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PLLM division factor needs to be set correctly to ensure that the VCO
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input frequency ranges from 1 to 2 MHz. It is recommended to select a
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frequency of 2 MHz to limit PLL jitter.
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Allowed values: 2-63
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "Multiplier factor for PLL VCO output clock"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 336
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range 192 432 if SOC_STM32F401XE
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range 50 432
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help
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PLLN multiplier factor needs to be set correctly to ensure that the
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VCO output frequency is between 100 and 432 MHz, except on STM32F401
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where the frequency must be between 192 and 432 MHz.
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Allowed values: 50-432 (STM32F401: 192-432)
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL division factor for main system clock"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 4
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range 2 8
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help
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PLLP division factor needs to be set correctly to not exceed 84MHz.
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Allowed values: 2, 4, 6, 8
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "Division factor for OTG FS, SDIO and RNG clocks"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 7
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range 2 15
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help
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The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
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need a frequency lower than or equal to 48 MHz to work correctly.
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Allowed values: 2-15
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endif # SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
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if SOC_SERIES_STM32L0X
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config CLOCK_STM32_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 4
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range 3 48
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help
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PLL multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48.
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PLL output must not exceed 96MHz(1.8V)/48MHz(1.5V)/24MHz(1.2V).
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config CLOCK_STM32_PLL_DIVISOR
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int "PLL divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 2 4
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help
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PLL divisor, allowed values: 2-4.
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endif # SOC_SERIES_STM32L0X
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if SOC_SERIES_STM32L4X
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config CLOCK_STM32_PLL_M_DIVISOR
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int "PLL divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 1
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range 1 8
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help
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PLL divisor, allowed values: 1-8. With this ensure that the PLL
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VCO input frequency ranges from 4 to 16MHz.
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 20
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range 8 86
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help
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PLL multiplier, allowed values: 2-16. PLL output must not
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exceed 344MHz.
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL P Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 7
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range 0 17
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help
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PLL P Output divisor, allowed values: 0, 7, 17.
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "PLL Q Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 0 8
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help
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PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.
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config CLOCK_STM32_PLL_R_DIVISOR
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int "PLL R Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 4
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range 0 8
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help
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PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.
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config CLOCK_STM32_LSE
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bool "Low-speed external clock"
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default n
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help
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Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
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crystal resonator oscillator.
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config CLOCK_STM32_MSI_PLL_MODE
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bool "MSI PLL MODE"
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depends on CLOCK_STM32_LSE
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default n
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help
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Enable hardware auto-calibration with LSE.
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endif # SOC_SERIES_STM32L4X
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config CLOCK_STM32_AHB_PRESCALER
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int "AHB prescaler"
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default 0
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range 0 512
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help
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AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128,
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256, 512.
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config CLOCK_STM32_APB1_PRESCALER
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int "APB1 prescaler"
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default 1
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range 1 16
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help
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APB1 Low speed clock (PCLK1) prescaler, allowed values:
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1, 2, 4, 8, 16
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if SOC_SERIES_STM32F0X!=y
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config CLOCK_STM32_APB2_PRESCALER
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int "APB2 prescaler"
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default 1
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range 1 16
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help
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APB2 High speed clock (PCLK2) prescaler, allowed values:
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1, 2, 4, 8, 16
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endif # SOC_SERIES_STM32F0X!=y
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choice
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prompt "STM32 MCO1 Clock Source"
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default CLOCK_STM32_MCO1_SRC_NOCLOCK
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config CLOCK_STM32_MCO1_SRC_NOCLOCK
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bool "NOCLOCK"
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help
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MCO1 output disabled, no clock on MCO1
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config CLOCK_STM32_MCO1_SRC_LSE
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bool "LSE"
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depends on SOC_SERIES_STM32F4X
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help
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Use LSE as source of MCO1
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config CLOCK_STM32_MCO1_SRC_HSE
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bool "HSE"
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depends on SOC_SERIES_STM32F4X
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help
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Use HSE as source of MCO1
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config CLOCK_STM32_MCO1_SRC_HSI
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bool "HSI"
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depends on SOC_SERIES_STM32F4X
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help
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Use HSI as source of MCO1
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config CLOCK_STM32_MCO1_SRC_PLLCLK
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bool "PLLCLK"
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depends on SOC_SERIES_STM32F4X
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help
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Use PLLCLK as source of MCO1
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endchoice
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config CLOCK_STM32_MCO1_DIV
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int "MCO1 prescaler"
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depends on !CLOCK_STM32_MCO1_SRC_NOCLOCK
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default 1
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range 1 5
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help
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allowed values: 1, 2, 3, 4, 5
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choice
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prompt "STM32 MCO2 Clock Source"
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default CLOCK_STM32_MCO2_SRC_NOCLOCK
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config CLOCK_STM32_MCO2_SRC_NOCLOCK
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bool "NOCLOCK"
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help
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MCO2 output disabled, no clock on MCO2
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config CLOCK_STM32_MCO2_SRC_SYSCLK
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bool "SYSCLK"
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depends on SOC_SERIES_STM32F4X
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help
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Use SYSCLK as source of MCO2
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config CLOCK_STM32_MCO2_SRC_PLLI2S
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bool "PLLI2S"
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depends on SOC_SERIES_STM32F4X
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help
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Use PLLI2S as source of MCO2
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config CLOCK_STM32_MCO2_SRC_HSE
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bool "HSE"
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depends on SOC_SERIES_STM32F4X
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help
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Use HSE as source of MCO2
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config CLOCK_STM32_MCO2_SRC_PLLCLK
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bool "PLLCLK"
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depends on SOC_SERIES_STM32F4X
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help
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Use PLLCLK as source of MCO2
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endchoice
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config CLOCK_STM32_MCO2_DIV
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int "MCO2 prescaler"
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depends on !CLOCK_STM32_MCO2_SRC_NOCLOCK
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default 1
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range 1 5
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help
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allowed values: 1, 2, 3, 4, 5
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endif # CLOCK_CONTROL_STM32_CUBE
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endif # SOC_FAMILY_STM32
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