480 lines
10 KiB
C
480 lines
10 KiB
C
/*
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* Copyright (c) 2018 Google LLC.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam0_nvmctrl
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#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(flash_sam0);
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#include <zephyr/device.h>
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#include <zephyr/drivers/flash.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <soc.h>
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#include <string.h>
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/*
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* Zephyr and the SAM0 series use different and conflicting names for
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* the erasable units and programmable units:
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*
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* The erase unit is a row, which is a 'page' in Zephyr terms.
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* The program unit is a page, which is a 'write_block' in Zephyr.
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*
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* This file uses the SAM0 names internally and the Zephyr names in
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* any error messages.
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*/
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/*
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* Number of lock regions. The number is fixed and the region size
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* grows with the flash size.
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*/
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#define LOCK_REGIONS DT_INST_PROP(0, lock_regions)
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#define LOCK_REGION_SIZE (FLASH_SIZE / LOCK_REGIONS)
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#if defined(NVMCTRL_BLOCK_SIZE)
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#define ROW_SIZE NVMCTRL_BLOCK_SIZE
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#elif defined(NVMCTRL_ROW_SIZE)
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#define ROW_SIZE NVMCTRL_ROW_SIZE
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#endif
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#define PAGES_PER_ROW (ROW_SIZE / FLASH_PAGE_SIZE)
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#define FLASH_MEM(_a) ((uint32_t *)((uint8_t *)((_a) + CONFIG_FLASH_BASE_ADDRESS)))
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struct flash_sam0_data {
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#if CONFIG_SOC_FLASH_SAM0_EMULATE_BYTE_PAGES
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uint8_t buf[ROW_SIZE];
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off_t offset;
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#endif
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#if defined(CONFIG_MULTITHREADING)
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struct k_sem sem;
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#endif
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};
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#if CONFIG_FLASH_PAGE_LAYOUT
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static const struct flash_pages_layout flash_sam0_pages_layout = {
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.pages_count = CONFIG_FLASH_SIZE * 1024 / ROW_SIZE,
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.pages_size = ROW_SIZE,
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};
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#endif
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static const struct flash_parameters flash_sam0_parameters = {
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#if CONFIG_SOC_FLASH_SAM0_EMULATE_BYTE_PAGES
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.write_block_size = 1,
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#else
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.write_block_size = DT_PROP(DT_INST(0, soc_nv_flash), write_block_size),
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#endif
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.erase_value = 0xff,
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};
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static int flash_sam0_write_protection(const struct device *dev, bool enable);
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static inline void flash_sam0_sem_take(const struct device *dev)
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{
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#if defined(CONFIG_MULTITHREADING)
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struct flash_sam0_data *ctx = dev->data;
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k_sem_take(&ctx->sem, K_FOREVER);
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#endif
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}
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static inline void flash_sam0_sem_give(const struct device *dev)
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{
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#if defined(CONFIG_MULTITHREADING)
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struct flash_sam0_data *ctx = dev->data;
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k_sem_give(&ctx->sem);
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#endif
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}
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static int flash_sam0_valid_range(off_t offset, size_t len)
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{
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if (offset < 0) {
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LOG_WRN("0x%lx: before start of flash", (long)offset);
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return -EINVAL;
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}
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if ((offset + len) > CONFIG_FLASH_SIZE * 1024) {
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LOG_WRN("0x%lx: ends past the end of flash", (long)offset);
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return -EINVAL;
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}
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return 0;
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}
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static void flash_sam0_wait_ready(void)
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{
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#ifdef NVMCTRL_STATUS_READY
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while (NVMCTRL->STATUS.bit.READY == 0) {
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}
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#else
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while (NVMCTRL->INTFLAG.bit.READY == 0) {
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}
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#endif
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}
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static int flash_sam0_check_status(off_t offset)
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{
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flash_sam0_wait_ready();
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#ifdef NVMCTRL_INTFLAG_PROGE
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NVMCTRL_INTFLAG_Type status = NVMCTRL->INTFLAG;
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/* Clear any flags */
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NVMCTRL->INTFLAG.reg = status.reg;
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#else
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NVMCTRL_STATUS_Type status = NVMCTRL->STATUS;
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/* Clear any flags */
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NVMCTRL->STATUS = status;
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#endif
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if (status.bit.PROGE) {
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LOG_ERR("programming error at 0x%lx", (long)offset);
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return -EIO;
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} else if (status.bit.LOCKE) {
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LOG_ERR("lock error at 0x%lx", (long)offset);
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return -EROFS;
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} else if (status.bit.NVME) {
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LOG_ERR("NVM error at 0x%lx", (long)offset);
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return -EIO;
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}
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return 0;
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}
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static int flash_sam0_write_page(const struct device *dev, off_t offset,
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const void *data)
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{
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const uint32_t *src = data;
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const uint32_t *end = src + FLASH_PAGE_SIZE / sizeof(*src);
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uint32_t *dst = FLASH_MEM(offset);
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int err;
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#ifdef NVMCTRL_CTRLA_CMD_PBC
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY;
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#else
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_PBC | NVMCTRL_CTRLB_CMDEX_KEY;
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#endif
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flash_sam0_wait_ready();
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/* Ensure writes happen 32 bits at a time. */
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for (; src != end; src++, dst++) {
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*dst = UNALIGNED_GET((uint32_t *)src);
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}
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#ifdef NVMCTRL_CTRLA_CMD_WP
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_WP | NVMCTRL_CTRLA_CMDEX_KEY;
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#else
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_WP | NVMCTRL_CTRLB_CMDEX_KEY;
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#endif
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err = flash_sam0_check_status(offset);
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if (err != 0) {
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return err;
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}
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if (memcmp(data, FLASH_MEM(offset), FLASH_PAGE_SIZE) != 0) {
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LOG_ERR("verify error at offset 0x%lx", (long)offset);
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return -EIO;
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}
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return 0;
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}
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static int flash_sam0_erase_row(const struct device *dev, off_t offset)
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{
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*FLASH_MEM(offset) = 0U;
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#ifdef NVMCTRL_CTRLA_CMD_ER
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_ER | NVMCTRL_CTRLA_CMDEX_KEY;
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#else
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_EB | NVMCTRL_CTRLB_CMDEX_KEY;
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#endif
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return flash_sam0_check_status(offset);
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}
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#if CONFIG_SOC_FLASH_SAM0_EMULATE_BYTE_PAGES
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static int flash_sam0_commit(const struct device *dev)
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{
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struct flash_sam0_data *ctx = dev->data;
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int err;
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int page;
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off_t offset = ctx->offset;
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ctx->offset = 0;
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if (offset == 0) {
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return 0;
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}
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err = flash_sam0_erase_row(dev, offset);
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if (err != 0) {
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return err;
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}
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for (page = 0; page < PAGES_PER_ROW; page++) {
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err = flash_sam0_write_page(
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dev, offset + page * FLASH_PAGE_SIZE,
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&ctx->buf[page * FLASH_PAGE_SIZE]);
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if (err != 0) {
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return err;
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}
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}
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return 0;
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}
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static int flash_sam0_write(const struct device *dev, off_t offset,
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const void *data, size_t len)
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{
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struct flash_sam0_data *ctx = dev->data;
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const uint8_t *pdata = data;
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off_t addr;
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int err;
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LOG_DBG("0x%lx: len %zu", (long)offset, len);
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err = flash_sam0_valid_range(offset, len);
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if (err != 0) {
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return err;
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}
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flash_sam0_sem_take(dev);
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err = flash_sam0_write_protection(dev, false);
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if (err == 0) {
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for (addr = offset; addr < offset + len; addr++) {
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off_t base = addr & ~(ROW_SIZE - 1);
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if (base != ctx->offset) {
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/* Started a new row. Flush any pending ones. */
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flash_sam0_commit(dev);
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memcpy(ctx->buf, (void *)base,
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sizeof(ctx->buf));
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ctx->offset = base;
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}
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ctx->buf[addr % ROW_SIZE] = *pdata++;
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}
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flash_sam0_commit(dev);
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}
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int err2 = flash_sam0_write_protection(dev, true);
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if (!err) {
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err = err2;
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}
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flash_sam0_sem_give(dev);
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return err;
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}
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#else /* CONFIG_SOC_FLASH_SAM0_EMULATE_BYTE_PAGES */
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static int flash_sam0_write(const struct device *dev, off_t offset,
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const void *data, size_t len)
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{
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const uint8_t *pdata = data;
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int err;
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size_t idx;
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err = flash_sam0_valid_range(offset, len);
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if (err != 0) {
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return err;
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}
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if ((offset % FLASH_PAGE_SIZE) != 0) {
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LOG_WRN("0x%lx: not on a write block boundary", (long)offset);
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return -EINVAL;
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}
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if ((len % FLASH_PAGE_SIZE) != 0) {
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LOG_WRN("%zu: not a integer number of write blocks", len);
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return -EINVAL;
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}
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flash_sam0_sem_take(dev);
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err = flash_sam0_write_protection(dev, false);
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if (err == 0) {
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for (idx = 0; idx < len; idx += FLASH_PAGE_SIZE) {
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err = flash_sam0_write_page(dev, offset + idx,
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&pdata[idx]);
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if (err != 0) {
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break;
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}
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}
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}
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int err2 = flash_sam0_write_protection(dev, true);
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if (!err) {
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err = err2;
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}
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flash_sam0_sem_give(dev);
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return err;
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}
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#endif
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static int flash_sam0_read(const struct device *dev, off_t offset, void *data,
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size_t len)
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{
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int err;
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err = flash_sam0_valid_range(offset, len);
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if (err != 0) {
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return err;
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}
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memcpy(data, (uint8_t *)CONFIG_FLASH_BASE_ADDRESS + offset, len);
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return 0;
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}
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static int flash_sam0_erase(const struct device *dev, off_t offset,
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size_t size)
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{
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int err;
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err = flash_sam0_valid_range(offset, ROW_SIZE);
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if (err != 0) {
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return err;
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}
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if ((offset % ROW_SIZE) != 0) {
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LOG_WRN("0x%lx: not on a page boundary", (long)offset);
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return -EINVAL;
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}
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if ((size % ROW_SIZE) != 0) {
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LOG_WRN("%zu: not a integer number of pages", size);
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return -EINVAL;
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}
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flash_sam0_sem_take(dev);
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err = flash_sam0_write_protection(dev, false);
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if (err == 0) {
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for (size_t addr = offset; addr < offset + size;
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addr += ROW_SIZE) {
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err = flash_sam0_erase_row(dev, addr);
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if (err != 0) {
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break;
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}
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}
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}
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int err2 = flash_sam0_write_protection(dev, true);
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if (!err) {
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err = err2;
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}
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flash_sam0_sem_give(dev);
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return err;
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}
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static int flash_sam0_write_protection(const struct device *dev, bool enable)
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{
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off_t offset;
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int err;
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for (offset = 0; offset < CONFIG_FLASH_SIZE * 1024;
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offset += LOCK_REGION_SIZE) {
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NVMCTRL->ADDR.reg = offset + CONFIG_FLASH_BASE_ADDRESS;
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#ifdef NVMCTRL_CTRLA_CMD_LR
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if (enable) {
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_LR |
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NVMCTRL_CTRLA_CMDEX_KEY;
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} else {
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_UR |
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NVMCTRL_CTRLA_CMDEX_KEY;
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}
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#else
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if (enable) {
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_LR |
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NVMCTRL_CTRLB_CMDEX_KEY;
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} else {
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NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_UR |
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NVMCTRL_CTRLB_CMDEX_KEY;
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}
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#endif
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err = flash_sam0_check_status(offset);
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if (err != 0) {
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goto done;
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}
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}
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done:
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return err;
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}
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#if CONFIG_FLASH_PAGE_LAYOUT
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void flash_sam0_page_layout(const struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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*layout = &flash_sam0_pages_layout;
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*layout_size = 1;
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}
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#endif
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static const struct flash_parameters *
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flash_sam0_get_parameters(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return &flash_sam0_parameters;
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}
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static int flash_sam0_init(const struct device *dev)
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{
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#if defined(CONFIG_MULTITHREADING)
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struct flash_sam0_data *ctx = dev->data;
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k_sem_init(&ctx->sem, 1, 1);
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#endif
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#ifdef PM_APBBMASK_NVMCTRL
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/* Ensure the clock is on. */
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PM->APBBMASK.bit.NVMCTRL_ = 1;
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#else
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MCLK->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
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#endif
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#ifdef NVMCTRL_CTRLB_MANW
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/* Require an explicit write command */
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NVMCTRL->CTRLB.bit.MANW = 1;
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#endif
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return flash_sam0_write_protection(dev, false);
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}
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static const struct flash_driver_api flash_sam0_api = {
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.erase = flash_sam0_erase,
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.write = flash_sam0_write,
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.read = flash_sam0_read,
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.get_parameters = flash_sam0_get_parameters,
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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.page_layout = flash_sam0_page_layout,
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#endif
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};
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static struct flash_sam0_data flash_sam0_data_0;
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DEVICE_DT_INST_DEFINE(0, flash_sam0_init, NULL,
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&flash_sam0_data_0, NULL, POST_KERNEL,
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CONFIG_FLASH_INIT_PRIORITY, &flash_sam0_api);
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