178 lines
3.7 KiB
C
178 lines
3.7 KiB
C
/*
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* Copyright (c) 2021 BrainCo Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_dac
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#include <errno.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/gd32.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/drivers/dac.h>
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#include <gd32_dac.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(dac_gd32, CONFIG_DAC_LOG_LEVEL);
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/**
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* GD32 DAC HAL use different DAC0 interface for 2 or 1 output channels SoCs.
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* Unify the DAC0 interface to DAC0_xx.
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*/
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#if DT_INST_PROP(0, num_channels) == 1
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#define DAC_CTL_DEN0 DAC_CTL_DEN
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#define DAC0_R8DH DAC_R8DH
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#define DAC0_R12DH DAC_R12DH
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#endif
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struct dac_gd32_config {
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uint32_t reg;
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uint16_t clkid;
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struct reset_dt_spec reset;
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const struct pinctrl_dev_config *pcfg;
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uint32_t num_channels;
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uint32_t reset_val;
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};
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struct dac_gd32_data {
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uint8_t resolutions[2];
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};
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static void dac_gd32_enable(uint8_t dacx)
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{
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switch (dacx) {
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case 0U:
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DAC_CTL |= DAC_CTL_DEN0;
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break;
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#if DT_INST_PROP(0, num_channels) == 2
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case 1U:
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DAC_CTL |= DAC_CTL_DEN1;
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break;
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#endif
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}
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}
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static void dac_gd32_disable(uint8_t dacx)
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{
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switch (dacx) {
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case 0U:
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DAC_CTL &= ~DAC_CTL_DEN0;
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break;
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#if DT_INST_PROP(0, num_channels) == 2
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case 1U:
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DAC_CTL &= ~DAC_CTL_DEN1;
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break;
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#endif
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}
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}
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static void dac_gd32_write(struct dac_gd32_data *data,
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uint8_t dacx, uint32_t value)
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{
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switch (dacx) {
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case 0U:
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if (data->resolutions[dacx] == 8U) {
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DAC0_R8DH = value;
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} else {
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DAC0_R12DH = value;
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}
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break;
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#if DT_INST_PROP(0, num_channels) == 2
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case 1U:
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if (data->resolutions[dacx] == 8U) {
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DAC1_R8DH = value;
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} else {
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DAC1_R12DH = value;
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}
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break;
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#endif
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}
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}
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static int dac_gd32_channel_setup(const struct device *dev,
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const struct dac_channel_cfg *channel_cfg)
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{
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struct dac_gd32_data *data = dev->data;
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const struct dac_gd32_config *config = dev->config;
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uint8_t dacx = channel_cfg->channel_id;
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if (dacx >= config->num_channels) {
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return -ENOTSUP;
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}
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/* GD32 DAC only support 8 or 12 bits resolution */
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if ((channel_cfg->resolution != 8U) &&
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(channel_cfg->resolution != 12U)) {
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LOG_ERR("Only 8 and 12 bits resolutions are supported!");
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return -ENOTSUP;
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}
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data->resolutions[dacx] = channel_cfg->resolution;
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dac_gd32_disable(dacx);
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dac_gd32_write(data, dacx, config->reset_val);
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dac_gd32_enable(dacx);
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return 0;
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}
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static int dac_gd32_write_value(const struct device *dev,
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uint8_t dacx, uint32_t value)
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{
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struct dac_gd32_data *data = dev->data;
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const struct dac_gd32_config *config = dev->config;
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if (dacx >= config->num_channels) {
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return -ENOTSUP;
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}
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dac_gd32_write(data, dacx, value);
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return 0;
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}
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struct dac_driver_api dac_gd32_driver_api = {
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.channel_setup = dac_gd32_channel_setup,
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.write_value = dac_gd32_write_value
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};
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static int dac_gd32_init(const struct device *dev)
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{
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const struct dac_gd32_config *cfg = dev->config;
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int ret;
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("Failed to apply pinctrl state");
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return ret;
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}
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(void)clock_control_on(GD32_CLOCK_CONTROLLER,
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(clock_control_subsys_t *)&cfg->clkid);
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(void)reset_line_toggle_dt(&cfg->reset);
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return 0;
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}
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PINCTRL_DT_INST_DEFINE(0);
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static struct dac_gd32_data dac_gd32_data_0;
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static const struct dac_gd32_config dac_gd32_cfg_0 = {
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.reg = DT_INST_REG_ADDR(0),
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.clkid = DT_INST_CLOCKS_CELL(0, id),
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.reset = RESET_DT_SPEC_INST_GET(0),
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
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.num_channels = DT_INST_PROP(0, num_channels),
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.reset_val = DT_INST_PROP(0, reset_val),
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};
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DEVICE_DT_INST_DEFINE(0, &dac_gd32_init, NULL, &dac_gd32_data_0,
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&dac_gd32_cfg_0, POST_KERNEL, CONFIG_DAC_INIT_PRIORITY,
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&dac_gd32_driver_api);
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