122 lines
3.1 KiB
ReStructuredText
122 lines
3.1 KiB
ReStructuredText
.. zephyr:code-sample:: fpga-controller
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:name: FPGA Controller
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Load a bitstream into an FPGA and perform basic operations on it.
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Overview
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********
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This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable or disable the FPGA.
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This sample demonstrates how to use the FPGA driver API and the FPGA controller shell subsystem.
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Currently the sample works with `Quicklogic Quickfeather board`_.
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Requirements
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************
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* Zephyr RTOS
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or
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* Zephyr RTOS with shell subsystem enabled (for shell application)
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* `Quicklogic Quickfeather board`_
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Building
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********
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For building on QuickLogic QuickFeather board:
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.. zephyr-app-commands::
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:zephyr-app: samples/drivers/fpga/fpga_controller
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:host-os: unix
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:board: quick_feather
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:goals: build
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To build the FPGA Controller shell application, use the supplied
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configuration file prj_shell.conf:
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.. zephyr-app-commands::
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:zephyr-app: samples/drivers/fpga/fpga_controller
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:host-os: unix
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:board: quick_feather
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:conf: prj_shell.conf
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:goals: build
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:compact:
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Running
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*******
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See :ref:`quickfeather` on how to load an image to the board.
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Sample output
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=============
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Once the board is programmed, the LED should alternately flash red and green.
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For the FPGA controller shell application, after connecting to the shell console you should see the following output:
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.. code-block:: console
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Address of the bitstream (red): 0xADDR
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Address of the bitstream (green): 0xADDR
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Size of the bitstream (red): 75960
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Size of the bitstream (green): 75960
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uart:~$
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This sample is already prepared with bitstreams.
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After executing the sample, you can see at what address it is stored and its size in bytes.
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The FPGA controller command can now be used (``fpga load <device> <address> <size in bytes>``):
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.. code-block:: console
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uart:~$ fpga load FPGA 0x2001a46c 75960
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FPGA: loading bitstream
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The LED should start blinking (color depending on the selected bitstream).
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To upload the bitstream again you need to reset the FPGA:
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.. code-block:: console
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uart:~$ fpga reset FPGA
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FPGA: resetting FPGA
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You can also use your own bitstream.
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To load a bitstream into device memory, use `devmem load` command.
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It is important to use the -e option when sending a bitstream via `xxd`:
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.. code-block:: console
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uart:~$ devmem load -e 0x10000
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Loading...
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Press ctrl-x + ctrl-q to stop
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Now, the loader is waiting for data.
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You can either type it directly from the console or send it from the host PC (replace `ttyX` with the appropriate one for your shell console):
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.. code-block:: console
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xxd -p data > /dev/ttyX
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(It is important to use plain-style hex dump)
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Once the data is transferred, use `ctrl-x + ctrl-q` to quit loader.
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It will print the sum of the read bytes and return to the shell:
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.. code-block:: console
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Number of bytes read: 75960
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uart:~$
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Now the bitstream can be uploaded again.
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.. code-block:: console
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uart:~$ fpga load FPGA 0x10000 75960
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FPGA: loading bitstream
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References
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**********
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.. _Quicklogic Quickfeather board:
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https://github.com/QuickLogic-Corp/quick-feather-dev-board
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