38 lines
709 B
Plaintext
38 lines
709 B
Plaintext
/*
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* Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
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* Copyright 2024, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_lpc55S16_ns.dtsi>
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#include "lpcxpresso55s16_common.dtsi"
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/ {
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model = "NXP LPCXpresso55S16 board";
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compatible = "nxp,lpc55xxx", "nxp,lpc";
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};
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/*
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* Default for this board is to allocate SRAM0-2 for data. But the
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* application can have an application specific device tree to
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* allocate the SRAMs differently.
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*/
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(64)>;
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};
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zephyr_udc0: &usbhs {
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status = "okay";
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phy_handle = <&usbphy1>;
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};
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&usbphy1 {
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status = "okay";
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tx-d-cal = <5>;
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tx-cal-45-dp-ohms = <10>;
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tx-cal-45-dm-ohms = <10>;
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};
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