124 lines
4.0 KiB
C
124 lines
4.0 KiB
C
/*
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* Copyright (c) 2011-2015 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file CPU power management code for IA-32
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*
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* DESCRIPTION
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* This module provides an implementation of the architecture-specific
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* nano_cpu_idle() primitive required by the nanokernel idle loop component.
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* It can be called within an implementation of _sys_power_save_idle(),
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* which is provided for the microkernel by the platform.
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*
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* The module also provides an implementation of nano_cpu_atomic_idle(), which
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* atomically re-enables interrupts and enters low power mode.
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*
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* INTERNAL
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* These implementations of nano_cpu_idle() and nano_cpu_atomic_idle() could be
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* used when operating as a Hypervisor guest. More specifically, the Hypervisor
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* supports the execution of the 'hlt' instruction from a guest (results in a
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* VM exit), and more importantly, the Hypervisor will respect the
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* single instruction delay slot after the 'sti' instruction as required
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* by nano_cpu_atomic_idle().
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*/
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#include <zephyr.h>
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#include <misc/kernel_event_logger.h>
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#include <arch/cpu.h>
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#ifdef CONFIG_BOOT_TIME_MEASUREMENT
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extern uint64_t __idle_tsc; /* timestamp when CPU went idle */
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#endif
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/**
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*
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* @brief Power save idle routine for IA-32
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*
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* This function will be called by the nanokernel idle loop or possibly within
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* an implementation of _sys_power_save_idle in the microkernel when the
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* '_sys_power_save_flag' variable is non-zero. The IA-32 'hlt' instruction
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* will be issued causing a low-power consumption sleep mode.
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*
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* @return N/A
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*/
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void nano_cpu_idle(void)
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{
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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_int_latency_stop();
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#endif
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_sys_k_event_logger_enter_sleep();
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#if defined(CONFIG_BOOT_TIME_MEASUREMENT)
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__idle_tsc = _NanoTscRead();
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#endif
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__asm__ volatile (
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"sti\n\t"
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"hlt\n\t");
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}
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/**
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*
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* @brief Atomically re-enable interrupts and enter low power mode
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*
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* This function is utilized by the nanokernel object "wait" APIs for tasks,
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* e.g. nano_task_lifo_get_wait(), nano_task_sem_take_wait(),
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* nano_task_stack_pop_wait(), and nano_task_fifo_get_wait().
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*
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* INTERNAL
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* The requirements for nano_cpu_atomic_idle() are as follows:
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* 1) The enablement of interrupts and entering a low-power mode needs to be
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* atomic, i.e. there should be no period of time where interrupts are
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* enabled before the processor enters a low-power mode. See the comments
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* in nano_task_lifo_get_wait(), for example, of the race condition that
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* occurs if this requirement is not met.
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*
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* 2) After waking up from the low-power mode, the interrupt lockout state
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* must be restored as indicated in the 'imask' input parameter.
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*
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* @return N/A
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*/
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void nano_cpu_atomic_idle(unsigned int imask)
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{
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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_int_latency_stop();
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#endif
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_sys_k_event_logger_enter_sleep();
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__asm__ volatile (
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"sti\n\t"
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/*
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* The following statement appears in "Intel 64 and IA-32
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* Architectures Software Developer's Manual", regarding the 'sti'
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* instruction:
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*
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* "After the IF flag is set, the processor begins responding to
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* external, maskable interrupts after the next instruction is
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* executed."
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*
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* Thus the IA-32 implementation of nano_cpu_atomic_idle() will
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* atomically re-enable interrupts and enter a low-power mode.
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*/
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"hlt\n\t");
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/* restore interrupt lockout state before returning to caller */
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if (!(imask & 0x200)) {
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#ifdef CONFIG_INT_LATENCY_BENCHMARK
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_int_latency_start();
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#endif
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__asm__ volatile("cli");
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}
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}
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