401 lines
9.5 KiB
C
401 lines
9.5 KiB
C
/*
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* Copyright (c) 2009-2011, 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief PCI bus support
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*
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*
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* This module implements the PCI H/W access functions.
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <pci/pci_mgr.h>
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#include <string.h>
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#include <soc.h>
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#if (PCI_CTRL_ADDR_REG == 0)
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#error "PCI_CTRL_ADDR_REG cannot be zero"
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#endif
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#if (PCI_CTRL_DATA_REG == 0)
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#error "PCI_CTRL_DATA_REG cannot be zero"
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#endif
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/**
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*
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* @brief Read a PCI controller register
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*
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* @param reg PCI register to read
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* @param data where to put the data
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* @param size size of the data to read (8/16/32 bits)
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*
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* This routine reads the specified register from the PCI controller and
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* places the data into the provided buffer.
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*
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* @return N/A
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*
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*/
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static void pci_ctrl_read(u32_t reg, u32_t *data, u32_t size)
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{
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/* read based on the size requested */
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switch (size) {
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/* long (32 bits) */
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case SYS_PCI_ACCESS_32BIT:
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*data = sys_in32(reg);
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break;
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/* word (16 bits) */
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case SYS_PCI_ACCESS_16BIT:
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*data = sys_in16(reg);
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break;
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/* byte (8 bits) */
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case SYS_PCI_ACCESS_8BIT:
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*data = sys_in8(reg);
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break;
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}
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}
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/**
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*
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* @brief Write a PCI controller register
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*
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* @param reg PCI register to write
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* @param data data to write
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* @param size size of the data to write (8/16/32 bits)
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*
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* This routine writes the provided data to the specified register in the PCI
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* controller.
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*
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* @return N/A
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*
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*/
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static void pci_ctrl_write(u32_t reg, u32_t data, u32_t size)
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{
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/* write based on the size requested */
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switch (size) {
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/* long (32 bits) */
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case SYS_PCI_ACCESS_32BIT:
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sys_out32(data, reg);
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break;
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/* word (16 bits) */
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case SYS_PCI_ACCESS_16BIT:
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sys_out16(data, reg);
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break;
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/* byte (8 bits) */
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case SYS_PCI_ACCESS_8BIT:
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sys_out8(data, reg);
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break;
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}
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}
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/**
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*
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* @brief Read the PCI controller data register
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*
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* @param controller controller number
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* @param offset is the offset within the data region
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* @param data is the returned data
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* @param size is the size of the data to read
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*
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* This routine reads the data register of the specified PCI controller.
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*
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* @return 0 or -1
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*
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*/
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static int pci_ctrl_data_read(u32_t controller, u32_t offset,
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u32_t *data, u32_t size)
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{
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/* we only support one controller */
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if (controller != DEFAULT_PCI_CONTROLLER) {
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return (-1);
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}
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pci_ctrl_read(PCI_CTRL_DATA_REG + offset, data, size);
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return 0;
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}
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/**
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*
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* @brief Write the PCI controller data register
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*
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* @param controller the controller number
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* @param offset is the offset within the address register
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* @param data is the data to write
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* @param size is the size of the data
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*
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* This routine writes the provided data to the data register of the
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* specified PCI controller.
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*
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* @return 0 or -1
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*
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*/
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static int pci_ctrl_data_write(u32_t controller, u32_t offset,
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u32_t data, u32_t size)
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{
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/* we only support one controller */
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if (controller != DEFAULT_PCI_CONTROLLER) {
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return (-1);
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}
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pci_ctrl_write(PCI_CTRL_DATA_REG + offset, data, size);
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return 0;
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}
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/**
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*
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* @brief Write the PCI controller address register
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*
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* @param controller is the controller number
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* @param offset is the offset within the address register
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* @param data is the data to write
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* @param size is the size of the data
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*
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* This routine writes the provided data to the address register of the
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* specified PCI controller.
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*
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* @return 0 or -1
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*
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*/
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static int pci_ctrl_addr_write(u32_t controller, u32_t offset,
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u32_t data, u32_t size)
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{
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/* we only support one controller */
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if (controller != DEFAULT_PCI_CONTROLLER) {
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return (-1);
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}
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pci_ctrl_write(PCI_CTRL_ADDR_REG + offset, data, size);
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return 0;
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}
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/**
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*
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* @brief Read a PCI register from a device
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*
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* This routine reads data from a PCI device's configuration space. The
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* device and register to read is specified by the address parameter ("addr")
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* and must be set appropriately by the caller. The address is defined by
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* the structure type pci_addr_t and contains the following members:
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*
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* bus: PCI bus number (0-255)
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* device: PCI device number (0-31)
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* func: device function number (0-7)
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* reg: device 32-bit register number to read (0-63)
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* offset: offset within 32-bit register to read (0-3)
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*
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* The size parameter specifies the number of bytes to read from the PCI
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* configuration space, valid values are 1, 2, and 4 bytes. A 32-bit value
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* is always returned but it will contain only the number of bytes specified
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* by the size parameter.
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*
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* If multiple PCI controllers are present in the system, the controller id
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* can be specified in the "controller" parameter. If only one controller
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* is present, the id DEFAULT_PCI_CONTROLLER can be used to denote this
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* controller.
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*
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* Example:
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*
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* union pci_addr_reg addr;
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* u32_t status;
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*
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* addr.field.bus = 0; /@ PCI bus zero @/
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* addr.field.device = 1; /@ PCI device one @/
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* addr.field.func = 0; /@ PCI function zero @/
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* addr.field.reg = 4; /@ PCI register 4 @/
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* addr.field.offset = 0; /@ PCI register offset @/
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*
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* pci_read (DEFAULT_PCI_CONTROLLER, addr, sizeof(u16_t), &status);
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*
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*
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* NOTE:
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* Reading of PCI data must be performed as an atomic operation. It is up to
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* the caller to enforce this.
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*
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* @param controller is the PCI controller number to use
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* @param addr is the PCI address to read
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* @param size is the size of the data in bytes
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* @param data is a pointer to the data read from the device
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*
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* @return N/A
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*
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*/
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void pci_read(u32_t controller, union pci_addr_reg addr,
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u32_t size, u32_t *data)
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{
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u32_t access_size;
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u32_t access_offset;
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/* validate the access size */
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switch (size) {
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case 1:
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access_size = SYS_PCI_ACCESS_8BIT;
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access_offset = addr.field.offset;
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break;
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case 2:
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access_size = SYS_PCI_ACCESS_16BIT;
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access_offset = addr.field.offset;
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break;
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case 4:
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default:
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access_size = SYS_PCI_ACCESS_32BIT;
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access_offset = 0U;
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break;
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}
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/* ensure enable has been set */
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addr.field.enable = 1;
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/* clear the offset for the address register */
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addr.field.offset = 0;
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/* read the data from the PCI controller */
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pci_ctrl_addr_write(
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controller, PCI_NO_OFFSET, addr.value, SYS_PCI_ACCESS_32BIT);
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pci_ctrl_data_read(controller, access_offset, data, access_size);
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}
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/**
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*
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* @brief Write a to a PCI register
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*
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* This routine writes data to a PCI device's configuration space. The
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* device and register to write is specified by the address parameter ("addr")
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* and must be set appropriately by the caller. The address is defined by
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* the structure type pci_addr_t and contains the following members:
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*
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* bus: PCI bus number (0-255)
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* device: PCI device number (0-31)
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* func: device function number (0-7)
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* reg: device register number to read (0-63)
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* offset: offset within 32-bit register to write (0-3)
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*
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* The size parameter specifies the number of bytes to write to the PCI
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* configuration space, valid values are 1, 2, and 4 bytes. A 32-bit value
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* is always provided but only the number of bytes specified by the size
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* parameter will be written to the device.
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*
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* If multiple PCI controllers are present in the system, the controller id
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* can be specified in the "controller" parameter. If only one controller
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* is present, the id DEFAULT_PCI_CONTROLLER can be used to denote this
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* controller.
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*
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* Example:
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*
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* pci_addr_t addr;
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* u32_t bar0 = 0xE0000000;
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*
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* addr.field.bus = 0; /@ PCI bus zero @/
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* addr.field.device = 1; /@ PCI device one @/
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* addr.field.func = 0; /@ PCI function zero @/
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* addr.field.reg = 16; /@ PCI register 16 @/
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* addr.field.offset = 0; /@ PCI register offset @/
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*
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* pci_write (DEFAULT_PCI_CONTROLLER, addr, sizeof(u32_t), bar0);
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*
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* NOTE:
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* Writing of PCI data must be performed as an atomic operation. It is up to
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* the caller to enforce this.
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*
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* @param controller is the PCI controller to use
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* @param addr is the PCI address to read
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* @param size is the size in bytes to write
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* @param data is the data to write
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*
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* @return N/A
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*
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*/
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void pci_write(u32_t controller, union pci_addr_reg addr,
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u32_t size, u32_t data)
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{
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u32_t access_size;
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u32_t access_offset;
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/* validate the access size */
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switch (size) {
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case 1:
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access_size = SYS_PCI_ACCESS_8BIT;
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access_offset = addr.field.offset;
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break;
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case 2:
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access_size = SYS_PCI_ACCESS_16BIT;
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access_offset = addr.field.offset;
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break;
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case 4:
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default:
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access_size = SYS_PCI_ACCESS_32BIT;
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access_offset = 0U;
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break;
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}
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/* ensure enable has been set */
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addr.field.enable = 1;
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/* clear the offset for the address register */
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addr.field.offset = 0;
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/* write the data to the PCI controller */
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pci_ctrl_addr_write(
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controller, PCI_NO_OFFSET, addr.value, SYS_PCI_ACCESS_32BIT);
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pci_ctrl_data_write(controller, access_offset, data, access_size);
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}
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/**
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*
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* @brief Get the PCI header for a device
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*
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* This routine reads the PCI header for the specified device and puts the
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* result in the supplied header structure.
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*
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* @return N/A
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*/
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void pci_header_get(u32_t controller,
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union pci_addr_reg pci_ctrl_addr,
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union pci_dev *pci_dev_header)
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{
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u32_t i;
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/* clear out the header */
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(void)memset(pci_dev_header, 0, sizeof(*pci_dev_header));
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/* fill in the PCI header from the device */
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for (i = 0U; i < PCI_HEADER_WORDS; i++) {
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pci_ctrl_addr.field.reg = i;
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pci_read(controller,
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pci_ctrl_addr,
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sizeof(u32_t),
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&pci_dev_header->words.word[i]);
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}
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}
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