93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc.h"
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/*
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* Instruction Cache definitions
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*/
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#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB)
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#define ESP32S2_ICACHE_SIZE CACHE_SIZE_8KB
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#else
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#define ESP32S2_ICACHE_SIZE CACHE_SIZE_16KB
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#endif
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#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B)
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#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_16B
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#else
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#define ESP32S2_ICACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#endif
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/*
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* Data Cache definitions
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*/
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#if defined(CONFIG_ESP32S2_DATA_CACHE_8KB)
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#define ESP32S2_DCACHE_SIZE CACHE_SIZE_8KB
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#else
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#define ESP32S2_DCACHE_SIZE CACHE_SIZE_16KB
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#endif
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#if defined(CONFIG_ESP32S2_DATA_CACHE_LINE_16B)
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#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_16B
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#else
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#define ESP32S2_DCACHE_LINE_SIZE CACHE_LINE_SIZE_32B
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#endif
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void IRAM_ATTR esp_config_instruction_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID,
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CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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#else
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
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CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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#endif
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cache_size = ESP32S2_ICACHE_SIZE;
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cache_ways = CACHE_4WAYS_ASSOC;
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cache_line_size = ESP32S2_ICACHE_LINE_SIZE;
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esp_rom_Cache_Suspend_ICache();
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esp_rom_Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
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esp_rom_Cache_Invalidate_ICache_All();
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esp_rom_Cache_Resume_ICache(0);
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}
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void IRAM_ATTR esp_config_data_cache_mode(void)
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{
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cache_size_t cache_size;
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cache_ways_t cache_ways;
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cache_line_size_t cache_line_size;
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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#if CONFIG_ESP32S2_DATA_CACHE_8KB
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
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CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
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#else
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_DCACHE_LOW,
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CACHE_MEMORY_DCACHE_HIGH, CACHE_MEMORY_INVALID);
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#endif
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#else
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#if CONFIG_ESP32S2_DATA_CACHE_8KB
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
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CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_INVALID);
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#else
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esp_rom_Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH,
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CACHE_MEMORY_DCACHE_LOW, CACHE_MEMORY_DCACHE_HIGH);
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#endif
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#endif
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cache_size = ESP32S2_DCACHE_SIZE;
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cache_ways = CACHE_4WAYS_ASSOC;
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cache_line_size = ESP32S2_DCACHE_LINE_SIZE;
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esp_rom_Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
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esp_rom_Cache_Invalidate_DCache_All();
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}
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