Immo Birnbaum 86d68e15e9 soc: arm: xilinx_zynq7000: add MMU PTEs for all AXI GPIO IP core instances ... add the MMU page table entries for all instances of the Xilinx AXI GPIO controller IP core. Other than any Zynq-7000 peripheral supported so far, the existance of 1..n instances of the IP core within the FPGA part of the SoC is optional. Therefore, other than addressing instances of supported peripherals using their DT node label as has always been the case so far, the data for the MMU page table is added using the DT_FOREACH_STATUS_OKAY macro. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>		2022-08-15 08:11:35 +00:00
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common	soc: arm: xilinx: zynq7000: add pinctrl header file	2022-06-28 20:46:11 +02:00
xc7zxxx	soc: arm: xilinx_zynq7000: add MMU PTEs for all AXI GPIO IP core instances	2022-08-15 08:11:35 +00:00
xc7zxxxs	soc: arm: xilinx_zynq7000: add MMU PTEs for all AXI GPIO IP core instances	2022-08-15 08:11:35 +00:00
CMakeLists.txt	soc: arm: xilinx: zynq7000: add pinctrl header file	2022-06-28 20:46:11 +02:00
Kconfig	…
Kconfig.defconfig	…
Kconfig.soc	…