71 lines
1.3 KiB
Plaintext
71 lines
1.3 KiB
Plaintext
/*
|
|
* Copyright (c) 2019 Nordic Semiconductor ASA
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
/* .dtsi header for nRF5340 CPUAPP (Application MCU), Non-Secure domain */
|
|
|
|
#include <arm/armv8-m.dtsi>
|
|
#include "nrf_common.dtsi"
|
|
|
|
/ {
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-m33f";
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mpu: mpu@e000ed90 {
|
|
compatible = "arm,armv8m-mpu";
|
|
reg = <0xe000ed90 0x40>;
|
|
};
|
|
};
|
|
};
|
|
|
|
chosen {
|
|
zephyr,entropy = &rng_hci;
|
|
zephyr,flash-controller = &flash_controller;
|
|
};
|
|
|
|
soc {
|
|
sram0: memory@20000000 {
|
|
compatible = "mmio-sram";
|
|
};
|
|
|
|
peripheral@40000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x40000000 0x10000000>;
|
|
|
|
/* Common nRF5340 Application MCU
|
|
* peripheral description
|
|
*/
|
|
#include "nrf5340_cpuapp_peripherals.dtsi"
|
|
};
|
|
};
|
|
|
|
/* Default IPC description */
|
|
ipc {
|
|
#include "nrf5340_cpuapp_ipc.dtsi"
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <3>;
|
|
};
|
|
|
|
/*
|
|
* Include the non-secure peripherals file here since
|
|
* it expects to be at the root level, adding a 'gpiote' label
|
|
* for the GPIOTE1 peripheral defined in that file which is
|
|
* always accessible as a non-secure peripheral.
|
|
*/
|
|
#include "nrf5340_cpuapp_peripherals_ns.dtsi"
|
|
gpiote: &gpiote1 {};
|