114 lines
2.1 KiB
Plaintext
114 lines
2.1 KiB
Plaintext
#include "skeleton.dtsi"
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#include <dt-bindings/i2c/i2c.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "LX6";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "LX6";
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reg = <1>;
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};
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core_intc: core_intc@0 {
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compatible = "xtensa,core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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sram0: memory@be000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xbe000000 0x300000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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cavs0: cavs@78800 {
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compatible = "intel,cavs-intc";
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reg = <0x78800 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <6 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs1: cavs@78810 {
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compatible = "intel,cavs-intc";
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reg = <0x78810 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0xA 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs2: cavs@78820 {
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compatible = "intel,cavs-intc";
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reg = <0x78820 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0XD 0 0>;
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interrupt-parent = <&core_intc>;
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};
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cavs3: cavs@78830 {
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compatible = "intel,cavs-intc";
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reg = <0x78830 0x10>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <0x10 0 0>;
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interrupt-parent = <&core_intc>;
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};
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dw_intc: intc@81800 {
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compatible = "snps,designware-intc";
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reg = <0x00081800 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <7 0 0>;
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interrupt-parent = <&cavs0>;
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};
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uart0: uart@80800 {
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compatible = "ns16550";
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reg = <0x80800 0x400>;
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label = "UART_0";
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clock-frequency = <38400000>;
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interrupts = <3 0 0>;
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interrupt-parent = <&dw_intc>;
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status = "disabled";
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};
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i2c0: i2c@80400 {
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compatible = "snps,designware-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80400 0x400>;
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interrupts = <2 0 0>;
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interrupt-parent = <&dw_intc>;
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label = "I2C_0";
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status = "disabled";
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};
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};
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};
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