598 lines
15 KiB
C
598 lines
15 KiB
C
/*
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* Copyright (c) 2016 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(spi_ll_stm32);
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#include <misc/util.h>
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#include <kernel.h>
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#include <board.h>
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#include <errno.h>
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#include <spi.h>
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#include <toolchain.h>
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#include <clock_control/stm32_clock_control.h>
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#include <clock_control.h>
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#include "spi_ll_stm32.h"
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#define DEV_CFG(dev) \
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(const struct spi_stm32_config * const)(dev->config->config_info)
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#define DEV_DATA(dev) \
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(struct spi_stm32_data * const)(dev->driver_data)
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/*
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* Check for SPI_SR_FRE to determine support for TI mode frame format
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* error flag, because STM32F1 SoCs do not support it and STM32CUBE
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* for F1 family defines an unused LL_SPI_SR_FRE.
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*/
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#if defined(LL_SPI_SR_UDR)
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#define SPI_STM32_ERR_MSK (LL_SPI_SR_UDR | LL_SPI_SR_CRCERR | LL_SPI_SR_MODF | \
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LL_SPI_SR_OVR | LL_SPI_SR_FRE)
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#elif defined(SPI_SR_FRE)
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#define SPI_STM32_ERR_MSK (LL_SPI_SR_CRCERR | LL_SPI_SR_MODF | \
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LL_SPI_SR_OVR | LL_SPI_SR_FRE)
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#else
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#define SPI_STM32_ERR_MSK (LL_SPI_SR_CRCERR | LL_SPI_SR_MODF | LL_SPI_SR_OVR)
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#endif
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/* Value to shift out when no application data needs transmitting. */
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#define SPI_STM32_TX_NOP 0x00
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static bool spi_stm32_transfer_ongoing(struct spi_stm32_data *data)
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{
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return spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx);
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}
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static int spi_stm32_get_err(SPI_TypeDef *spi)
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{
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u32_t sr = LL_SPI_ReadReg(spi, SR);
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if (sr & SPI_STM32_ERR_MSK) {
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LOG_ERR("%s: err=%d", __func__,
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sr & (u32_t)SPI_STM32_ERR_MSK);
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/* OVR error must be explicitly cleared */
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if (LL_SPI_IsActiveFlag_OVR(spi)) {
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LL_SPI_ClearFlag_OVR(spi);
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}
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return -EIO;
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}
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return 0;
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}
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static inline u16_t spi_stm32_next_tx(struct spi_stm32_data *data)
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{
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u16_t tx_frame = SPI_STM32_TX_NOP;
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if (spi_context_tx_buf_on(&data->ctx)) {
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if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
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tx_frame = UNALIGNED_GET((u8_t *)(data->ctx.tx_buf));
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} else {
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tx_frame = UNALIGNED_GET((u16_t *)(data->ctx.tx_buf));
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}
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}
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return tx_frame;
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}
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/* Shift a SPI frame as master. */
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static void spi_stm32_shift_m(SPI_TypeDef *spi, struct spi_stm32_data *data)
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{
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u16_t tx_frame;
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u16_t rx_frame;
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tx_frame = spi_stm32_next_tx(data);
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while (!LL_SPI_IsActiveFlag_TXE(spi)) {
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/* NOP */
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}
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if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
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LL_SPI_TransmitData8(spi, tx_frame);
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/* The update is ignored if TX is off. */
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spi_context_update_tx(&data->ctx, 1, 1);
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} else {
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LL_SPI_TransmitData16(spi, tx_frame);
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/* The update is ignored if TX is off. */
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spi_context_update_tx(&data->ctx, 2, 1);
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}
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while (!LL_SPI_IsActiveFlag_RXNE(spi)) {
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/* NOP */
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}
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if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
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rx_frame = LL_SPI_ReceiveData8(spi);
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if (spi_context_rx_buf_on(&data->ctx)) {
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UNALIGNED_PUT(rx_frame, (u8_t *)data->ctx.rx_buf);
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}
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spi_context_update_rx(&data->ctx, 1, 1);
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} else {
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rx_frame = LL_SPI_ReceiveData16(spi);
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if (spi_context_rx_buf_on(&data->ctx)) {
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UNALIGNED_PUT(rx_frame, (u16_t *)data->ctx.rx_buf);
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}
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spi_context_update_rx(&data->ctx, 2, 1);
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}
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}
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/* Shift a SPI frame as slave. */
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static void spi_stm32_shift_s(SPI_TypeDef *spi, struct spi_stm32_data *data)
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{
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if (LL_SPI_IsActiveFlag_TXE(spi) && spi_context_tx_on(&data->ctx)) {
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u16_t tx_frame = spi_stm32_next_tx(data);
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if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
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LL_SPI_TransmitData8(spi, tx_frame);
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spi_context_update_tx(&data->ctx, 1, 1);
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} else {
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LL_SPI_TransmitData16(spi, tx_frame);
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spi_context_update_tx(&data->ctx, 2, 1);
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}
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} else {
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LL_SPI_DisableIT_TXE(spi);
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}
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if (LL_SPI_IsActiveFlag_RXNE(spi) && spi_context_rx_buf_on(&data->ctx)) {
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u16_t rx_frame;
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if (SPI_WORD_SIZE_GET(data->ctx.config->operation) == 8) {
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rx_frame = LL_SPI_ReceiveData8(spi);
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UNALIGNED_PUT(rx_frame, (u8_t *)data->ctx.rx_buf);
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spi_context_update_rx(&data->ctx, 1, 1);
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} else {
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rx_frame = LL_SPI_ReceiveData16(spi);
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UNALIGNED_PUT(rx_frame, (u16_t *)data->ctx.rx_buf);
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spi_context_update_rx(&data->ctx, 2, 1);
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}
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}
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}
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/*
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* Without a FIFO, we can only shift out one frame's worth of SPI
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* data, and read the response back.
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*
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* TODO: support 16-bit data frames.
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*/
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static int spi_stm32_shift_frames(SPI_TypeDef *spi, struct spi_stm32_data *data)
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{
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u16_t operation = data->ctx.config->operation;
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if (SPI_OP_MODE_GET(operation) == SPI_OP_MODE_MASTER) {
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spi_stm32_shift_m(spi, data);
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} else {
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spi_stm32_shift_s(spi, data);
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}
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return spi_stm32_get_err(spi);
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}
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static void spi_stm32_complete(struct spi_stm32_data *data, SPI_TypeDef *spi,
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int status)
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{
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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LL_SPI_DisableIT_TXE(spi);
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LL_SPI_DisableIT_RXNE(spi);
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LL_SPI_DisableIT_ERR(spi);
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#endif
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spi_context_cs_control(&data->ctx, false);
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#if defined(CONFIG_SPI_STM32_HAS_FIFO)
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/* Flush RX buffer */
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while (LL_SPI_IsActiveFlag_RXNE(spi)) {
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(void) LL_SPI_ReceiveData8(spi);
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}
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#endif
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if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
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while (LL_SPI_IsActiveFlag_BSY(spi)) {
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/* NOP */
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}
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}
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LL_SPI_Disable(spi);
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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spi_context_complete(&data->ctx, status);
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#endif
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}
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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static void spi_stm32_isr(void *arg)
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{
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struct device * const dev = (struct device *) arg;
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const struct spi_stm32_config *cfg = dev->config->config_info;
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struct spi_stm32_data *data = dev->driver_data;
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SPI_TypeDef *spi = cfg->spi;
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int err;
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err = spi_stm32_get_err(spi);
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if (err) {
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spi_stm32_complete(data, spi, err);
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return;
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}
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if (spi_stm32_transfer_ongoing(data)) {
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err = spi_stm32_shift_frames(spi, data);
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}
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if (err || !spi_stm32_transfer_ongoing(data)) {
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spi_stm32_complete(data, spi, err);
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}
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}
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#endif
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static int spi_stm32_configure(struct device *dev,
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const struct spi_config *config)
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{
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const struct spi_stm32_config *cfg = DEV_CFG(dev);
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struct spi_stm32_data *data = DEV_DATA(dev);
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const u32_t scaler[] = {
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LL_SPI_BAUDRATEPRESCALER_DIV2,
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LL_SPI_BAUDRATEPRESCALER_DIV4,
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LL_SPI_BAUDRATEPRESCALER_DIV8,
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LL_SPI_BAUDRATEPRESCALER_DIV16,
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LL_SPI_BAUDRATEPRESCALER_DIV32,
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LL_SPI_BAUDRATEPRESCALER_DIV64,
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LL_SPI_BAUDRATEPRESCALER_DIV128,
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LL_SPI_BAUDRATEPRESCALER_DIV256
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};
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SPI_TypeDef *spi = cfg->spi;
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u32_t clock;
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int br;
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if (spi_context_configured(&data->ctx, config)) {
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/* Nothing to do */
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return 0;
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}
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if ((SPI_WORD_SIZE_GET(config->operation) != 8)
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&& (SPI_WORD_SIZE_GET(config->operation) != 16)) {
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return -ENOTSUP;
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}
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clock_control_get_rate(device_get_binding(STM32_CLOCK_CONTROL_NAME),
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(clock_control_subsys_t) &cfg->pclken, &clock);
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for (br = 1 ; br <= ARRAY_SIZE(scaler) ; ++br) {
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u32_t clk = clock >> br;
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if (clk <= config->frequency) {
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break;
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}
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}
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if (br > ARRAY_SIZE(scaler)) {
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LOG_ERR("Unsupported frequency %uHz, max %uHz, min %uHz",
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config->frequency,
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clock >> 1,
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clock >> ARRAY_SIZE(scaler));
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return -EINVAL;
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}
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LL_SPI_Disable(spi);
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LL_SPI_SetBaudRatePrescaler(spi, scaler[br - 1]);
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) {
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LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_HIGH);
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} else {
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LL_SPI_SetClockPolarity(spi, LL_SPI_POLARITY_LOW);
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}
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if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) {
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LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_2EDGE);
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} else {
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LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_1EDGE);
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}
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LL_SPI_SetTransferDirection(spi, LL_SPI_FULL_DUPLEX);
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if (config->operation & SPI_TRANSFER_LSB) {
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LL_SPI_SetTransferBitOrder(spi, LL_SPI_LSB_FIRST);
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} else {
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LL_SPI_SetTransferBitOrder(spi, LL_SPI_MSB_FIRST);
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}
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LL_SPI_DisableCRC(spi);
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if (config->operation & SPI_OP_MODE_SLAVE) {
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LL_SPI_SetMode(spi, LL_SPI_MODE_SLAVE);
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} else {
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LL_SPI_SetMode(spi, LL_SPI_MODE_MASTER);
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}
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if (config->cs) {
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LL_SPI_SetNSSMode(spi, LL_SPI_NSS_SOFT);
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} else {
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if (config->operation & SPI_OP_MODE_SLAVE) {
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LL_SPI_SetNSSMode(spi, LL_SPI_NSS_HARD_INPUT);
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} else {
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LL_SPI_SetNSSMode(spi, LL_SPI_NSS_HARD_OUTPUT);
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}
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}
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if (SPI_WORD_SIZE_GET(config->operation) == 8) {
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LL_SPI_SetDataWidth(spi, LL_SPI_DATAWIDTH_8BIT);
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} else {
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LL_SPI_SetDataWidth(spi, LL_SPI_DATAWIDTH_16BIT);
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}
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#if defined(CONFIG_SPI_STM32_HAS_FIFO)
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LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER);
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#endif
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#ifndef CONFIG_SOC_SERIES_STM32F1X
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LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_MOTOROLA);
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#endif
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/* At this point, it's mandatory to set this on the context! */
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data->ctx.config = config;
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spi_context_cs_configure(&data->ctx);
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LOG_DBG("Installed config %p: freq %uHz (div = %u),"
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" mode %u/%u/%u, slave %u",
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config, clock >> br, 1 << br,
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(SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) ? 1 : 0,
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(SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) ? 1 : 0,
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(SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) ? 1 : 0,
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config->slave);
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return 0;
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}
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static int spi_stm32_release(struct device *dev,
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const struct spi_config *config)
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{
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struct spi_stm32_data *data = DEV_DATA(dev);
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static int transceive(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool asynchronous, struct k_poll_signal *signal)
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{
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const struct spi_stm32_config *cfg = DEV_CFG(dev);
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struct spi_stm32_data *data = DEV_DATA(dev);
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SPI_TypeDef *spi = cfg->spi;
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int ret;
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if (!tx_bufs && !rx_bufs) {
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return 0;
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}
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#ifndef CONFIG_SPI_STM32_INTERRUPT
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if (asynchronous) {
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return -ENOTSUP;
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}
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#endif
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spi_context_lock(&data->ctx, asynchronous, signal);
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ret = spi_stm32_configure(dev, config);
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if (ret) {
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return ret;
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}
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/* Set buffers info */
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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#if defined(CONFIG_SPI_STM32_HAS_FIFO)
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/* Flush RX buffer */
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while (LL_SPI_IsActiveFlag_RXNE(spi)) {
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(void) LL_SPI_ReceiveData8(spi);
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}
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#endif
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LL_SPI_Enable(spi);
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/* This is turned off in spi_stm32_complete(). */
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spi_context_cs_control(&data->ctx, true);
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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LL_SPI_EnableIT_ERR(spi);
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if (rx_bufs) {
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LL_SPI_EnableIT_RXNE(spi);
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}
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LL_SPI_EnableIT_TXE(spi);
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ret = spi_context_wait_for_completion(&data->ctx);
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#else
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do {
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ret = spi_stm32_shift_frames(spi, data);
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} while (!ret && spi_stm32_transfer_ongoing(data));
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spi_stm32_complete(data, spi, ret);
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#ifdef CONFIG_SPI_SLAVE
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if (spi_context_is_slave(&data->ctx) && !ret) {
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ret = data->ctx.recv_frames;
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}
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#endif /* CONFIG_SPI_SLAVE */
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#endif
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spi_context_release(&data->ctx, ret);
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return ret;
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}
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static int spi_stm32_transceive(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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return transceive(dev, config, tx_bufs, rx_bufs, false, NULL);
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}
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#ifdef CONFIG_SPI_ASYNC
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static int spi_stm32_transceive_async(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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struct k_poll_signal *async)
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{
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return transceive(dev, config, tx_bufs, rx_bufs, true, async);
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}
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#endif /* CONFIG_SPI_ASYNC */
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static const struct spi_driver_api api_funcs = {
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.transceive = spi_stm32_transceive,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_stm32_transceive_async,
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#endif
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.release = spi_stm32_release,
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};
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static int spi_stm32_init(struct device *dev)
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{
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struct spi_stm32_data *data __attribute__((unused)) = dev->driver_data;
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const struct spi_stm32_config *cfg = dev->config->config_info;
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__ASSERT_NO_MSG(device_get_binding(STM32_CLOCK_CONTROL_NAME));
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clock_control_on(device_get_binding(STM32_CLOCK_CONTROL_NAME),
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(clock_control_subsys_t) &cfg->pclken);
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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cfg->irq_config(dev);
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#endif
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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#ifdef CONFIG_SPI_1
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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static void spi_stm32_irq_config_func_1(struct device *port);
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#endif
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static const struct spi_stm32_config spi_stm32_cfg_1 = {
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.spi = (SPI_TypeDef *) CONFIG_SPI_1_BASE_ADDRESS,
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.pclken = {
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#ifdef CONFIG_SOC_SERIES_STM32F0X
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.enr = LL_APB1_GRP2_PERIPH_SPI1,
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.bus = STM32_CLOCK_BUS_APB1_2
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|
#else
|
|
.enr = LL_APB2_GRP1_PERIPH_SPI1,
|
|
.bus = STM32_CLOCK_BUS_APB2
|
|
#endif
|
|
},
|
|
#ifdef CONFIG_SPI_STM32_INTERRUPT
|
|
.irq_config = spi_stm32_irq_config_func_1,
|
|
#endif
|
|
};
|
|
|
|
static struct spi_stm32_data spi_stm32_dev_data_1 = {
|
|
SPI_CONTEXT_INIT_LOCK(spi_stm32_dev_data_1, ctx),
|
|
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_1, ctx),
|
|
};
|
|
|
|
DEVICE_AND_API_INIT(spi_stm32_1, CONFIG_SPI_1_NAME, &spi_stm32_init,
|
|
&spi_stm32_dev_data_1, &spi_stm32_cfg_1,
|
|
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
|
|
&api_funcs);
|
|
|
|
#ifdef CONFIG_SPI_STM32_INTERRUPT
|
|
static void spi_stm32_irq_config_func_1(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CONFIG_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
|
|
spi_stm32_isr, DEVICE_GET(spi_stm32_1), 0);
|
|
irq_enable(CONFIG_SPI_1_IRQ);
|
|
}
|
|
#endif
|
|
|
|
#endif /* CONFIG_SPI_1 */
|
|
|
|
#ifdef CONFIG_SPI_2
|
|
|
|
#ifdef CONFIG_SPI_STM32_INTERRUPT
|
|
static void spi_stm32_irq_config_func_2(struct device *port);
|
|
#endif
|
|
|
|
static const struct spi_stm32_config spi_stm32_cfg_2 = {
|
|
.spi = (SPI_TypeDef *) CONFIG_SPI_2_BASE_ADDRESS,
|
|
.pclken = {
|
|
.enr = LL_APB1_GRP1_PERIPH_SPI2,
|
|
.bus = STM32_CLOCK_BUS_APB1
|
|
},
|
|
#ifdef CONFIG_SPI_STM32_INTERRUPT
|
|
.irq_config = spi_stm32_irq_config_func_2,
|
|
#endif
|
|
};
|
|
|
|
static struct spi_stm32_data spi_stm32_dev_data_2 = {
|
|
SPI_CONTEXT_INIT_LOCK(spi_stm32_dev_data_2, ctx),
|
|
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_2, ctx),
|
|
};
|
|
|
|
DEVICE_AND_API_INIT(spi_stm32_2, CONFIG_SPI_2_NAME, &spi_stm32_init,
|
|
&spi_stm32_dev_data_2, &spi_stm32_cfg_2,
|
|
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
|
|
&api_funcs);
|
|
|
|
#ifdef CONFIG_SPI_STM32_INTERRUPT
|
|
static void spi_stm32_irq_config_func_2(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CONFIG_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI,
|
|
spi_stm32_isr, DEVICE_GET(spi_stm32_2), 0);
|
|
irq_enable(CONFIG_SPI_2_IRQ);
|
|
}
|
|
#endif
|
|
|
|
#endif /* CONFIG_SPI_2 */
|
|
|
|
#ifdef CONFIG_SPI_3
|
|
|
|
#ifdef CONFIG_SPI_STM32_INTERRUPT
|
|
static void spi_stm32_irq_config_func_3(struct device *port);
|
|
#endif
|
|
|
|
static const struct spi_stm32_config spi_stm32_cfg_3 = {
|
|
.spi = (SPI_TypeDef *) CONFIG_SPI_3_BASE_ADDRESS,
|
|
.pclken = {
|
|
.enr = LL_APB1_GRP1_PERIPH_SPI3,
|
|
.bus = STM32_CLOCK_BUS_APB1
|
|
},
|
|
#ifdef CONFIG_SPI_STM32_INTERRUPT
|
|
.irq_config = spi_stm32_irq_config_func_3,
|
|
#endif
|
|
};
|
|
|
|
static struct spi_stm32_data spi_stm32_dev_data_3 = {
|
|
SPI_CONTEXT_INIT_LOCK(spi_stm32_dev_data_3, ctx),
|
|
SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_3, ctx),
|
|
};
|
|
|
|
DEVICE_AND_API_INIT(spi_stm32_3, CONFIG_SPI_3_NAME, &spi_stm32_init,
|
|
&spi_stm32_dev_data_3, &spi_stm32_cfg_3,
|
|
POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
|
|
&api_funcs);
|
|
|
|
#ifdef CONFIG_SPI_STM32_INTERRUPT
|
|
static void spi_stm32_irq_config_func_3(struct device *dev)
|
|
{
|
|
IRQ_CONNECT(CONFIG_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI,
|
|
spi_stm32_isr, DEVICE_GET(spi_stm32_3), 0);
|
|
irq_enable(CONFIG_SPI_3_IRQ);
|
|
}
|
|
#endif
|
|
|
|
#endif /* CONFIG_SPI_3 */
|