134 lines
3.7 KiB
C
134 lines
3.7 KiB
C
/* quark_se_clock_control.c - Clock controller driver for Quark SE */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include <board.h>
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#include <device.h>
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#include <init.h>
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#include <sys_io.h>
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#include <clock_control.h>
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#include <clock_control/quark_se_clock_control.h>
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(clock_control);
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#ifdef CONFIG_ARC
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#define WRITE(__data, __base_address) \
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sys_out32(__data, __base_address)
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#define TEST_CLEAR_BIT(__base_address, __bit) \
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sys_io_test_and_clear_bit(__base_address, __bit)
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#else
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#define WRITE(__data, __base_address) \
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sys_write32(__data, __base_address)
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#define TEST_CLEAR_BIT(__base_address, __bit) \
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sys_test_and_clear_bit(__base_address, __bit)
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#endif /* CONFIG_ARC */
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struct quark_se_clock_control_config {
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u32_t base_address;
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};
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static inline int quark_se_clock_control_on(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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const struct quark_se_clock_control_config *info =
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dev->config->config_info;
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u32_t subsys = POINTER_TO_INT(sub_system);
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if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) {
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LOG_DBG("Enabling all clock gates on dev %p", dev);
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WRITE(0xffffffff, info->base_address);
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return 0;
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}
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LOG_DBG("Enabling clock gate on dev %p subsystem %u", dev, subsys);
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return TEST_CLEAR_BIT(info->base_address, subsys);
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}
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static inline int quark_se_clock_control_off(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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const struct quark_se_clock_control_config *info =
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dev->config->config_info;
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u32_t subsys = POINTER_TO_INT(sub_system);
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if (sub_system == CLOCK_CONTROL_SUBSYS_ALL) {
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LOG_DBG("Disabling all clock gates on dev %p", dev);
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WRITE(0x00000000, info->base_address);
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return 0;
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}
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LOG_DBG("clock gate on dev %p subsystem %u", dev, subsys);
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return TEST_CLEAR_BIT(info->base_address, subsys);
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}
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static const struct clock_control_driver_api quark_se_clock_control_api = {
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.on = quark_se_clock_control_on,
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.off = quark_se_clock_control_off,
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.get_rate = NULL,
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};
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int quark_se_clock_control_init(struct device *dev)
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{
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LOG_DBG("Quark_SE clock controller on: %p", dev);
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return 0;
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}
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#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL
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static struct quark_se_clock_control_config clock_quark_se_peripheral_config = {
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.base_address = CLOCK_PERIPHERAL_BASE_ADDR
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};
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DEVICE_AND_API_INIT(clock_quark_se_peripheral,
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CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME,
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&quark_se_clock_control_init,
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NULL, &clock_quark_se_peripheral_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&quark_se_clock_control_api);
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#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL */
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#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL
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static struct quark_se_clock_control_config clock_quark_se_external_config = {
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.base_address = CLOCK_EXTERNAL_BASE_ADDR
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};
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DEVICE_AND_API_INIT(clock_quark_se_external,
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CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME,
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&quark_se_clock_control_init,
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NULL, &clock_quark_se_external_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&quark_se_clock_control_api);
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#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL */
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#ifdef CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR
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static struct quark_se_clock_control_config clock_quark_se_sensor_config = {
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.base_address = CLOCK_SENSOR_BASE_ADDR
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};
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DEVICE_AND_API_INIT(clock_quark_se_sensor,
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CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME,
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&quark_se_clock_control_init,
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NULL, &clock_quark_se_sensor_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&quark_se_clock_control_api);
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#endif /* CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR */
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