133 lines
2.7 KiB
C
133 lines
2.7 KiB
C
/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/irq.h>
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#include <zephyr/drivers/entropy.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <stm32_ll_rng.h>
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#include "bleplat.h"
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#include "bpka.h"
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#include "linklayer_plat.h"
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(ble_plat);
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RAMCFG_HandleTypeDef hramcfg_SRAM1;
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const struct device *rng_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_entropy));
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struct entropy_stm32_rng_dev_data {
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RNG_TypeDef *rng;
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};
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struct entropy_stm32_rng_dev_cfg {
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struct stm32_pclken *pclken;
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};
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void BLEPLAT_Init(void)
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{
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BPKA_Reset();
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rng_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_entropy));
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if (!device_is_ready(rng_dev)) {
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LOG_ERR("error: random device not ready");
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}
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}
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void BLEPLAT_RngGet(uint8_t n, uint32_t *val)
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{
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LINKLAYER_PLAT_GetRNG((uint8_t *)val, 4 * n);
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}
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int BLEPLAT_PkaStartP256Key(const uint32_t *local_private_key)
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{
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return BPKA_StartP256Key(local_private_key);
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}
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void BLEPLAT_PkaReadP256Key(uint32_t *local_public_key)
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{
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BPKA_ReadP256Key(local_public_key);
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}
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int BLEPLAT_PkaStartDhKey(const uint32_t *local_private_key,
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const uint32_t *remote_public_key)
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{
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return BPKA_StartDhKey(local_private_key, remote_public_key);
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}
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int BLEPLAT_PkaReadDhKey(uint32_t *dh_key)
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{
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return BPKA_ReadDhKey(dh_key);
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}
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void BPKACB_Complete(void)
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{
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BLEPLATCB_PkaComplete();
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}
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void MX_RAMCFG_Init(void)
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{
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/* Initialize RAMCFG SRAM1 */
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hramcfg_SRAM1.Instance = RAMCFG_SRAM1;
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if (HAL_RAMCFG_Init(&hramcfg_SRAM1) != HAL_OK) {
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LOG_ERR("Could not init RAMCFG");
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}
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}
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void Error_Handler(void)
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{
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LOG_ERR("");
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}
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void enable_rng_clock(bool enable)
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{
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const struct entropy_stm32_rng_dev_cfg *dev_cfg = rng_dev->config;
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struct entropy_stm32_rng_dev_data *dev_data = rng_dev->data;
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struct stm32_pclken *rng_pclken;
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const struct device *rcc;
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unsigned int key;
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rcc = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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rng_pclken = (clock_control_subsys_t)&dev_cfg->pclken[0];
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key = irq_lock();
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/* Enable/Disable RNG clock only if not in use */
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if (!LL_RNG_IsEnabled((RNG_TypeDef *)dev_data->rng)) {
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if (enable) {
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clock_control_on(rcc, rng_pclken);
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} else {
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clock_control_off(rcc, rng_pclken);
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}
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}
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irq_unlock(key);
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}
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/* PKA IP requires RNG clock to be enabled
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* These APIs are used by BLE controller to enable/disable RNG clock,
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* based on PKA needs.
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*/
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void HW_RNG_DisableClock(uint8_t user_mask)
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{
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ARG_UNUSED(user_mask);
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enable_rng_clock(false);
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}
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void HW_RNG_EnableClock(uint8_t user_mask)
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{
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ARG_UNUSED(user_mask);
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enable_rng_clock(true);
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}
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/* BLE ctlr should not disable HSI on its own */
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void SCM_HSI_CLK_OFF(void) {}
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