120 lines
3.8 KiB
C
120 lines
3.8 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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#include <system_timer.h>
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/* STATUS register */
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#define ALTERA_AVALON_TIMER_STATUS_REG 0
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#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1)
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#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0)
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#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2)
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#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1)
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/* CONTROL register */
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#define ALTERA_AVALON_TIMER_CONTROL_REG 1
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#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1)
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#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0)
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#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2)
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#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1)
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#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4)
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#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2)
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#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8)
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#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3)
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/* Period and SnapShot Register for COUNTER_SIZE = 32 */
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/*----------------------------------------------------*/
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/* PERIODL register */
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#define ALTERA_AVALON_TIMER_PERIODL_REG 2
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#define ALTERA_AVALON_TIMER_PERIODL_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIODL_OFST (0)
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/* PERIODH register */
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#define ALTERA_AVALON_TIMER_PERIODH_REG 3
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#define ALTERA_AVALON_TIMER_PERIODH_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIODH_OFST (0)
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/* SNAPL register */
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#define ALTERA_AVALON_TIMER_SNAPL_REG 4
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#define ALTERA_AVALON_TIMER_SNAPL_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAPL_OFST (0)
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/* SNAPH register */
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#define ALTERA_AVALON_TIMER_SNAPH_REG 5
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#define ALTERA_AVALON_TIMER_SNAPH_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAPH_OFST (0)
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static u32_t accumulated_cycle_count;
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static void timer_irq_handler(void *unused)
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{
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ARG_UNUSED(unused);
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/* Clear the interrupt */
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_STATUS_REG,
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0);
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accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
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_sys_clock_tick_announce();
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}
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#ifdef CONFIG_TICKLESS_IDLE
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#error "Tickless idle not yet implemented for Avalon timer"
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#endif
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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#if TIMER_0_FIXED_PERIOD
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#error "Can't set timer period!"
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#else
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_PERIODL_REG,
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sys_clock_hw_cycles_per_tick & 0xFFFF);
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_PERIODH_REG,
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(sys_clock_hw_cycles_per_tick >> 16) & 0xFFFF);
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#endif
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IRQ_CONNECT(TIMER_0_IRQ, 0, timer_irq_handler, NULL, 0);
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irq_enable(TIMER_0_IRQ);
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/* Initial configuration: Generate interrupts, run continuously,
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* start running
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*/
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_CONTROL_REG,
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ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
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ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
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ALTERA_AVALON_TIMER_CONTROL_START_MSK);
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return 0;
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}
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u32_t _timer_cycle_get_32(void)
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{
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/* XXX Per the Altera Embedded IP Peripherals guide, you cannot
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* use a timer instance for both the system clock and timestamps
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* at the same time.
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*
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* Having this function return accumulated_cycle_count + get_snapshot()
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* does not work reliably. It's possible for the current countdown
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* to reset to the next interval before the timer interrupt is
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* delivered (and accumulated cycle count gets updated). The result
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* is an unlucky call to this function will appear to jump backward
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* in time.
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*
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* To properly obtain timestamps, the CPU must be configured with
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* a second timer peripheral instance that is configured to
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* count down from some large initial 64-bit value. This
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* is currently unimplemented.
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*/
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return accumulated_cycle_count;
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}
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