642fc7ad54
The kernel coherence cache flush code was using a scratch register to mark the top of the stack. Likewise a good candidate for ZSR use. Signed-off-by: Andy Ross <andrew.j.ross@intel.com> |
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kernel_arch_func.h | ||
offsets_short_arch.h | ||
xtensa-asm2-context.h | ||
xtensa-asm2-s.h | ||
xtensa-asm2.h |